Supervia Etch Stop Openings for Precise Multi-Level Via Alignment

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Solution Overview

Problem

The challenges in semiconductor fabrication include precise dimension control and alignment issues in forming vias, particularly when etching through multiple metal-containing etch stop layers, which can lead to resistance and reliability concerns, especially in supervias that connect non-adjacent metal levels.

Innovation Solution

A method is employed to form supervias by using a supervia etch mask to create openings in etch stop layers before applying a masking layer, ensuring precise alignment and minimizing damage to patterned layers, even with metal-containing etch stop layers, thereby reducing resistance and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching methods are used to form vias through metal-containing etch stop layers, then the etching process can be completed, but alignment precision deteriorates and resistance increases

Engineering Contradiction:
Improvevia alignment precisionVSAvoidvia connection reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming openings in the etch stop layer before depositing the supervia mask layer. This preliminary opening formation allows subsequent alignment steps to reference the pre-formed openings, ensuring precise via placement while preventing mask damage during etching through metal-containing layers.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If etching is performed through multiple metal-containing etch stop layers, then supervias connecting non-adjacent metal levels can be formed, but resistance and reliability concerns worsen

Engineering Contradiction:
Improvesupervia connection capabilityVSAvoidvia connection reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent forms openings in etch stop layers before mask deposition to establish precise pathways through multiple metal-containing layers. This preliminary action ensures that subsequent etching follows predetermined paths, maintaining low resistance and high reliability even when connecting non-adjacent metal levels through multiple etch stop layers.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If a masking layer is applied before etching through metal-containing etch stop layers, then the etching process can be controlled, but the patterned layers suffer damage

Engineering Contradiction:
Improveetching process controlVSAvoidmask damage
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional sequence by forming etch stop layer openings before depositing the masking layer. This inversion eliminates the need for the mask to protect against metal-containing etch stop layer etching, as those openings are already formed. The mask only needs to protect the final via etching step, significantly reducing mask damage and extending mask life.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the formation of supervias by maintaining precise alignment and reducing resistance and reliability risks, allowing for more efficient and reliable connections between non-adjacent metal levels in semiconductor devices.

Implementation Method 1

forming openings in the first metal-containing etch stop layer using a first supervia mask... forming openings in the second metal-containing etch stop layer using the first supervia mask... etching a supervia opening from the third metal layer to the first metal layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS12438038B2Forming vias in a semiconductor device
Publication Date: 2025.10.07 TOKYO ELECTRON LTD
  • US12438038B2 patent drawing
  • US12438038B2 patent drawing
  • US12438038B2 patent drawing

AI summary

In certain embodiments, a method includes forming a first etch stop layer on a first metallization layer of a semiconductor substrate. The method further includes forming, prior to forming a second metallization layer over the first metallization layer, an opening in the first etch stop layer according to a supervia mask. The method further includes forming the second metallization layer over the first metallization layer and forming a second etch stop layer on the second metallization layer. The method further includes forming, prior to forming a third metallization layer over the second metallization layer, an opening in the second etch stop layer according to the supervia mask. The method further includes forming the third metallization layer over the second metallization layer and etching a supervia opening from the third metallization layer to the first metallization layer according to the supervia mask.