Supervisor Thread Managing Worker Threads in Multi-Threaded Processor

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Solution Overview

Problem

Multi-threaded processors face challenges in efficiently coordinating the execution of concurrent threads, as existing solutions either require significant hardware duplication for parallelism or lack efficiency in code density with a fully software approach.

Innovation Solution

A processor architecture that includes an execution unit interleaving threads across a shared pipeline, utilizing a supervisor thread to manage worker threads through a set of context register sets, with dedicated instructions for relinquishing and returning time slots, enabling flexible and efficient thread coordination without excessive hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dedicated hardware is used to coordinate thread execution, then coordination efficiency is improved, but silicon footprint increases

Engineering Contradiction:

Improvethread coordination efficiencyVSAvoidsilicon footprint

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

A supervisor thread is introduced as an intermediary software component that coordinates worker threads through controlled access to a shared execution pipeline. The supervisor thread manages time slot allocation and thread switching, providing efficient coordination without requiring dedicated hardware coordination circuits, thus resolving the contradiction between coordination efficiency and silicon footprint.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces dedicated hardware coordination mechanisms with a software-based supervisor thread that uses standard processor instructions to manage thread execution. This substitution eliminates the need for additional coordination hardware while maintaining effective thread management through software-controlled time slot allocation and context switching.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If a fully software approach is used for thread coordination, then flexibility is improved, but code density efficiency deteriorates

Engineering Contradiction:

Improvethread management flexibilityVSAvoidcode density

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The execution pipeline is segmented into discrete time slots that are allocated to different threads through structured supervisor instructions. This segmentation provides flexibility in thread management while maintaining code density efficiency through systematic control of execution intervals and deterministic time slot allocation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The supervisor thread operates periodically by allocating time slots in a structured, repeating sequence to worker threads. This periodic execution pattern provides flexible thread management through configurable time slot intervals while maintaining efficient code density through predictable, rhythmic supervisor operations.

Inventive Principle:

Principle #19Periodic action

3Speed

If multiple execution pipelines are provided for parallelism, then execution speed is improved, but hardware duplication increases

Engineering Contradiction:

Improvethread execution speedVSAvoidhardware duplication

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Multiple worker threads are merged into a single shared execution pipeline, with the supervisor thread orchestrating their execution through time slot allocation. This merging approach maintains parallelism and execution speed by interleaving multiple threads in one pipeline, while eliminating hardware duplication by removing the need for separate execution pipelines for each thread.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

A single execution pipeline is designed to be universal and multi-functional, capable of executing any worker thread through supervisor-managed context switching. This universal pipeline replaces multiple dedicated pipelines, maintaining the ability to execute multiple threads in parallel while eliminating hardware duplication through resource sharing.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11550591B2Scheduling tasks in a multi-threaded processor

Publication Date: 2023.01.10 GRAPHCORE LTD

AI summary

A processor comprising: an execution unit for executing a respective thread in each of a repeating sequence of time slots; and a plurality of context register sets, each comprising a respective set of registers for representing a state of a respective thread. The context register sets comprise a respective worker context register set for each of the number of time slots the execution unit is operable to interleave, and at least one extra context register set. The worker context register sets represent the respective states of worker threads and the extra context register set being represents the state of a supervisor thread. The processor is configured to begin running the supervisor thread in each of the time slots, and to enable the supervisor thread to then individually relinquish each of the time slots in which it is running to a respective one of the worker threads.