Supervisory MMU for Secure Multi-Processor Memory Access
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Solution Overview
Problem
Conventional CPU architectures with single-tier memory management units lack the capability to securely manage access to non-volatile memory across multiple processing entities, failing to provide adequate address translation and permission control for preserving data integrity and trust levels between different processors.
Innovation Solution
A supervisory memory management unit (MMU) performs a second-tier address translation from physical to storage addresses, controlling access permissions and handling faults, thereby enabling secure access to a common memory storage area by multiple processing units while protecting data from less trusted entities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-tier MMU is used for memory management, then the device complexity is low, but the security and permission control capability for multi-processor access is insufficient
Solution Approach 1:
The memory management function is segmented into two independent tiers: the first-tier MMU in each CPU handles virtual-to-physical address translation, while the supervisory MMU handles physical-to-storage address translation and permission control. This segmentation allows each tier to specialize in specific functions, improving security without requiring a complete redesign of the entire memory management system.
Solution Approach 2:
The supervisory MMU acts as an intermediary between the first-tier MMUs and the shared non-volatile memory. It receives physical addresses from multiple CPUs, performs second-tier translation to storage addresses, and enforces permission controls before granting memory access. This intermediary structure enables centralized security management while maintaining CPU independence.
2Reliability
If multiple processing units access a common memory storage area directly, then the access speed is high, but data protection from less trusted entities is compromised
Solution Approach 1:
The supervisory MMU serves as a trusted intermediary that all CPU access requests must pass through. It maintains trust levels for different CPU entities and enforces permission controls based on these trust levels. This intermediary approach protects data in the shared non-volatile memory from less trusted entities while still allowing efficient access from trusted CPUs.
Solution Approach 2:
Different permission controls and trust level requirements are applied to different access patterns and CPU entities. The supervisory MMU can grant higher permissions to trusted CPUs while restricting access from less trusted entities, enabling fine-grained security control tailored to specific access scenarios rather than applying uniform restrictions to all access.
3Reliability
If each CPU performs its own address translation to shared memory, then the access efficiency is high, but the capability to control permissions and protect data is insufficient
Solution Approach 1:
The address translation function is divided into two segments: first-tier MMU handles virtual-to-physical translation at each CPU, while the supervisory MMU handles physical-to-storage translation centrally. This segmentation enables permission control to be concentrated in the supervisory MMU, which has a global view of all CPU entities and their trust levels, without eliminating the translation efficiency benefits of distributed first-tier MMUs.
Solution Approach 2:
The supervisory MMU performs multiple functions: it acts as a second-tier address translation unit, a permission control authority, and a trust level enforcement mechanism. By consolidating these functions in a single supervisory entity, the system achieves comprehensive permission control capability without requiring each CPU to implement complex security management independently.
4Reliability
If a supervisory MMU is introduced for second-tier address translation, then the security and data protection capability is improved, but the device complexity increases
Solution Approach 1:
The memory management architecture is segmented into two independent but coordinated tiers. The first-tier MMUs remain relatively simple units focused on virtual-to-physical translation, while the supervisory MMU handles the more complex physical-to-storage translation and permission control. This segmentation distributes complexity appropriately rather than concentrating all complexity in a single unit or spreading it uniformly across all CPUs.
Solution Approach 2:
The supervisory MMU merges multiple critical functions into a single entity: address translation, permission control, and trust level enforcement. This merging reduces the overall system complexity by eliminating the need for each CPU to independently implement these functions, while still providing comprehensive security and control capabilities through centralized management.
Data Source
AI summary
A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.