Supply-Switched Dual Cell Memory Bitcell Design
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Solution Overview
Problem
Existing Spin Transfer Torque Random Access Memory (STTRAM) bitcells require multiple signal lines for read and write operations, which limits cell size shrinkage and introduces layout restrictions and instability in bitcell operations.
Innovation Solution
A supply-switched dual cell memory bitcell design that eliminates the source or select line signal line, using a meshed supply line grid for increased reliability and stability, allowing read and write operations with reduced signal lines by coupling a supply line to a common node to drive complementary currents through resistance state storage cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple signal lines are used for read and write operations in existing STTRAM bitcells, then read and write operations can be performed, but cell size shrinkage is limited and layout restrictions increase
Solution Approach 1:
The patent extracts and eliminates the source or select line signal line from the STTRAM bitcell architecture. By removing this dedicated signal line and repurposing the supply line to perform both power delivery and select functionality through supply switching, the bitcell achieves reduced signal line count enabling cell size shrinkage while maintaining full read and write operational capability
Solution Approach 2:
The supply line is given multi-functionality by enabling it to serve both as a power supply line and as a select line for bitcell activation. Through supply switching mechanisms, the same physical line performs multiple functions: delivering power during normal operation and enabling selective access during read/write operations, thereby eliminating the need for separate select lines
2Ease of operation
If multiple signal lines are used for read and write operations in existing STTRAM bitcells, then read and write operations can be performed, but layout restrictions increase
Solution Approach 1:
The patent extracts and eliminates the source or select line signal line from the STTRAM bitcell architecture. By removing this dedicated signal line and repurposing the supply line to perform both power delivery and select functionality through supply switching, the bitcell achieves reduced signal line count enabling cell size shrinkage while maintaining full read and write operational capability
Solution Approach 2:
The supply line is given multi-functionality by enabling it to serve both as a power supply line and as a select line for bitcell activation. Through supply switching mechanisms, the same physical line performs multiple functions: delivering power during normal operation and enabling selective access during read/write operations, thereby eliminating the need for separate select lines
3Ease of operation
If multiple signal lines are used for read and write operations in existing STTRAM bitcells, then read and write operations can be performed, but operational stability decreases
Solution Approach 1:
The patent introduces supply switch transistors as intermediary elements that control the connection between the supply line and the bitcell. These switch transistors act as mediators that enable stable and controlled supply line switching, ensuring that the supply line can reliably perform both power delivery and select functions without causing operational instability or interference with read/write operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design facilitates cell size shrinkage, enhances operational reliability, and improves read margins by eliminating the need for select line signal lines, thereby increasing the stability and accuracy of bitcell operations.
Implementation Method 1
A supply switch transistor has an input coupled to a second word line signal line and is configured to couple the common node to the supply line when activated
Implementation Method 2
each complementary resistance state storage cell having a storage cell switch transistor having an input coupled to the first word line signal line, and a resistance state ferromagnetic device coupled in series with the storage cell switch transistor
Implementation Method 3
Spin Transfer Torque (STT) is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction (MTJ) device can be modified using a spin-polarized current
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
In one embodiment, a bit state in a supply-switched dual cell memory bitcell in accordance with the present description, may be read by coupling a supply line to a common node of the bitcell to drive complementary currents through complementary resistance state storage cells for a pair of complementary bit line signal lines of the bitcell. The bit state of the bitcell may be read by sensing complementary bit state signals on the pair of first and second complementary bit line signal lines. In one embodiment, each resistance state storage cell has a resistance state ferromagnetic device such as a magnetic-tunneling junction (MTJ). In one embodiment, a supply-switched dual cell memory bitcell in accordance with the present description may lack a source or select line (SL) signal line. Other aspects are described herein.