Supply Voltage Supervisor Reset Output Control Circuit
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Solution Overview
Problem
Existing supply voltage supervisors (SVS) face challenges in ensuring a low power-on reset voltage (VPOR) to prevent false resets during the power-on phase, especially when the supply voltage is high, as they require a threshold voltage to activate the output transistor, which can lead to the load exiting its reset state prematurely.
Innovation Solution
The proposed SVS design includes a series connection of transistors with an output node control circuit that actively pulls the reset output low at supply voltages lower than the threshold voltage of the second transistor, using a combination of transistors and resistors to ensure the reset signal is maintained low until the supply voltage reaches a predetermined threshold, thereby reducing the VPOR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a threshold voltage is used to activate the output transistor in existing SVS designs, then the circuit can detect supply voltage levels, but the load may exit its reset state prematurely during the power-on phase
Solution Approach 1:
The circuit performs preliminary action by actively pulling the reset output low through the third transistor before the supply voltage reaches the threshold level. This preliminary action ensures that the reset state is established early in the power-on sequence, preventing premature exit from reset even though the voltage detection mechanism is ready. The third transistor activates at lower voltages to maintain reset stability before the main output transistor can reliably activate.
2Productivity
If the supply voltage ramps up during power-on, then the system can be initialized, but loads may be in indeterminate states until the voltage reaches a certain level
Solution Approach 1:
The circuit applies preliminary anti-action by proactively asserting the reset signal low during the voltage ramp-up phase, counteracting the potential for indeterminate load states. The third transistor provides this counter-action by maintaining a low reset output even when the supply voltage is still rising and before the main output transistor activates. This prevents the load from entering or remaining in indeterminate states during the transition period.
3Power
If existing SVS designs are used with high supply voltages, then the system can operate, but false resets may occur due to insufficient VPOR control
Solution Approach 1:
The third transistor serves as an intermediary element between the supply voltage and the reset output. It mediates the voltage relationship by actively pulling the reset output low at voltages lower than the main output transistor's threshold. This intermediary action ensures proper VPOR control even when the main supply voltage is high, preventing false resets by decoupling the reset assertion timing from the main voltage level.
Data Source
AI summary
A circuit includes a first transistor including first and second current terminals. The first current terminal couples to a supply voltage node. A second transistor includes a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at an output node and the fourth current terminal couples to a ground node. A third transistor includes a third control input and fifth and sixth current terminals. The fifth current terminal couples to the output node and the sixth current terminal couples to the ground node. A fourth transistor includes a fourth control input and seventh and eighth current terminals. The eighth current terminal couples to the ground node and the seventh current terminal couples to the third control input. An inverter having an input coupled to the second control input and an output coupled to the fourth control input.