Support Pillar Structures for Leakage Reduction in 3D Memory
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Solution Overview
Problem
Three-dimensional vertical NAND strings face issues with word line leakage current due to damage from reaction ion etch processes and insufficient mechanical strength in support pillar structures, leading to degradation in device performance.
Innovation Solution
A monolithic three-dimensional memory device is developed with a support pillar structure that includes a dummy semiconductor channel with a narrower width than the memory opening fill structure, extending through all layers of the second alternating stack, and a method of forming this structure involves creating alternating stacks of insulating and conductive layers, forming memory and support openings, and filling them with semiconductor channels and memory films, respectively, to reduce leakage current and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If reaction ion etch processes are used to form memory stack structures, then etching precision is improved, but word line leakage current increases due to damage to dummy memory films
Solution Approach 1:
A support pillar structure is introduced as an intermediary element between the substrate and the memory stack. This support pillar includes a dummy semiconductor channel and a dummy memory film, where the dummy memory film serves as a protective intermediary that prevents direct damage to the word line during etching processes, thereby reducing leakage current while maintaining etching precision
Solution Approach 2:
The support pillar structure is formed beforehand to provide mechanical support and protection. The dummy memory film within the support pillar acts as a cushioning layer that absorbs etching damage before it can reach the actual word line, preventing leakage current issues before they occur
2Ease of manufacture
If support pillar structures are made with standard width, then ease of manufacture is maintained, but mechanical strength is insufficient causing structural deformations
Solution Approach 1:
The support pillar structure is constructed as a composite element containing both a dummy semiconductor channel and a dummy memory film. This composite structure provides enhanced mechanical strength and structural stability to prevent deformations during processing, while still being manufacturable using standard fabrication processes
3Strength
If support pillar structures are made with larger width, then mechanical strength is improved, but device complexity increases
Solution Approach 1:
The support pillar structure is segmented into distinct functional components: a dummy semiconductor channel portion and a dummy memory film portion. This segmentation allows each component to be optimized for its specific function while maintaining overall structural strength, and the segmented design can be integrated into existing memory device architectures without significantly increasing overall device complexity
Data Source
AI summary
Multiple tier structures including a respective alternating stack of insulating layers and electrically conductive layers is formed over a substrate. A memory opening fill structure extends through the alternating stacks, and includes a vertical semiconductor channel and a memory film. A support pillar structure extends through at least an upper alternating stack, and includes a dummy memory film and a dummy memory film. The support pillar structure may be narrower than the memory opening fill structure at a bottommost layer of the upper alternating stack. Additionally or alternatively, the dummy memory film may be located above a horizontal plane including a topmost surface of a lower alternating stack. Optionally, another support pillar structure including a dielectric material may be provided underneath the support pillar structure in the lower alternating stack. A dielectric material can be provided at levels of the lower alternating stack in a support pillar structure to reduce inter-level leakage current.


