Supported Capacitor Electrode Structure for Low-Leakage High-k Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in achieving high dielectric constant and low leakage current due to reduced unit cell area and operating voltage, requiring advanced materials and fabrication methods.
Innovation Solution
A semiconductor device is fabricated with a high dielectric constant and low leakage current by forming a capacitor structure that includes a lower electrode supported by a multi-level dielectric supporter and protective layer patterns, with an amorphous protective layer pattern between the supporter and the electrode, and a lower-level protective layer pattern between the electrode and the substrate, using specific materials like silicon nitride and niobium for enhanced structural stability and surface roughness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-k materials are used to increase capacitance, then dielectric constant is improved, but leakage current increases
Solution Approach 1:
The patent employs a composite dielectric structure consisting of a lower-level dielectric layer (high-k material such as HfO2, ZrO2, or Ta2O5) and an upper-level dielectric layer (low-k material such as SiO2 or Si3N4). This composite approach allows the device to achieve high capacitance through the high-k material while the low-k material suppresses leakage current, thereby resolving the contradiction between increasing capacitance and reducing leakage current.
2Productivity
If unit cell area is decreased to increase integration, then device density is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent divides the dielectric layer into two separate layers with distinct functions: the lower-level dielectric layer optimized for capacitance (high-k material) and the upper-level dielectric layer optimized for leakage suppression (low-k material). This segmentation allows each layer to be independently optimized for its specific function, maintaining manufacturing precision even as unit cell area decreases and device density increases.
3Manufacturing precision
If protective layer is fully formed on opening walls, then surface roughness is improved, but device complexity increases
Solution Approach 1:
The patent applies the protective layer selectively only to the sidewalls of the opening where it is needed for surface roughness control, rather than forming a complete continuous layer. The protective layer is deposited on the inner sidewalls of the opening to protect the lower electrode during subsequent etching processes, providing local protection and surface quality improvement without requiring a fully continuous protective structure throughout the entire device.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.