Surface Code Compilation via Disjoint Tree Weighting

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Solution Overview

Problem

Quantum computing faces challenges in manipulating a large number of qubits beyond their coherence time, requiring error corrections, particularly in implementing surface code architectures efficiently.

Innovation Solution

A method is proposed to optimize the implementation of quantum circuits by constructing a graph with disjoint trees and associating weights, selecting non-intersecting subsets for efficient rotation gate implementation, and generating a directed acyclic graph to minimize time steps, using a count strategy to maximize parallel computation and reduce calculation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If quantum error correction is implemented using surface code architecture, then reliability of quantum information storage is improved, but calculation time and processing efficiency deteriorate

Engineering Contradiction:
Improvequantum information storage reliabilityVSAvoidcalculation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the quantum circuit implementation into multiple layers and identifies independent commuting subsets of operations. By dividing the circuit into layers where operations within each layer can be executed in parallel, the method reduces the total number of sequential time steps while maintaining error correction requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary analysis to identify commuting subsets and construct the layered structure before actual circuit execution. By pre-processing the circuit to determine which operations can be grouped together and executed simultaneously, the method optimizes the implementation plan to minimize calculation time.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If more qubits are manipulated beyond coherence time, then computational capability is improved, but error correction complexity increases

Engineering Contradiction:
Improvecomputational capabilityVSAvoiderror correction complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple quantum operations that commute with each other into single parallel execution steps. By combining compatible operations from different parts of the circuit into the same layer, the method reduces the total number of time steps required while maintaining all necessary error correction operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the temporal parameter of operation execution by reorganizing the circuit from sequential to parallel execution where possible. By identifying commuting operators and grouping them into simultaneous execution layers, the method effectively changes the time parameter without altering the quantum logic or error correction requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230297868A1Compilation technique for surface code architecture
Publication Date: 2023.09.21 BULL SA
  • US20230297868A1 patent drawing
  • US20230297868A1 patent drawing
  • US20230297868A1 patent drawing

AI summary

Method for implementing a graph (G) comprising a plurality of vertices (V) and links (E) between the vertices, a set (R) being a collection of subsets (Ri) of said a given number of vertices (Rik) comprising:in said set (R), selecting subsets (Ri, Rj), called pre-selected subsets, such that a tree (Ti, Tj) is associated respectively to said subset (Ri, Rj), said associated trees (Ti, Tj) being pairwise disjoint and constructing (301) each tree (Ti);associating a weight to each said tree (Ti);choosing the subset for which the tree (Ti) has the highest weight.