Surface-Implanted Transistor Structure for Low-Dark-Current Pixels

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Transistor terminals in image sensor pixels experience high dark current and fixed pattern noise, degrading pixel performance and image quality due to high temporal and/or fixed pattern noise.

Innovation Solution

The implementation of transistor structures with a patterned or blanket surface implant region in the substrate, featuring lightly doped implant regions and a heavily doped surface implant layer, reduces dark current and fixed pattern noise by minimizing junction electric field effects and gate-induced drain leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transistor terminals are used to integrate and store photodiode-generated charge, then charge integration and storage capability is improved, but dark current increases causing high temporal and fixed pattern noise

Engineering Contradiction:
Improvecharge integration and storage capabilityVSAvoiddark current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating a surface implant layer with specific doping characteristics only in the source and drain regions of the transistor. This localized modification changes the electrical properties at these critical interfaces, reducing dark current generation at the semiconductor-silicon dioxide interface without affecting other regions of the transistor structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the doping parameters by forming a surface implant layer with heavy doping concentration (greater than 10^19 atoms/cm³) in the source and drain regions. This parameter change modifies the carrier concentration and electric field distribution at the interface, thereby reducing dark current while maintaining the charge storage capability of the transistor terminals.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If transistor terminals integrate and store charge, then pixel charge handling capability is improved, but fixed pattern noise increases degrading image quality

Engineering Contradiction:
Improvecharge handling capabilityVSAvoidimage quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The surface implant layer is selectively formed only in the source and drain regions, creating local quality improvements at these interfaces. This localized treatment reduces fixed pattern noise by minimizing interface effects at the charge storage terminals without requiring modification of the entire transistor structure, thereby preserving image quality while maintaining charge handling capability.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the performance of image sensor pixels by reducing dark current and fixed pattern noise, thereby improving image quality and pixel performance.

Implementation Method 1

a heavily doped surface implant layer in the substrate and overlapping the lightly doped implant region

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 2

minimizing junction electric field effects and gate-induced drain leakage

Methodology Applied
Scientific EffectElectric Field Effect: Electric Field

Data Source

PatentUS11881492B2Transistor structures
Publication Date: 2024.01.23 SEMICON COMPONENTS IND LLC
  • US11881492B2 patent drawing
  • US11881492B2 patent drawing
  • US11881492B2 patent drawing

AI summary

Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.