Surface-Emitting Laser Tunnel Junction for Lower Voltage Drop
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Solution Overview
Problem
Conventional surface emitting lasers experience significant voltage drops at the tunnel junction, limiting their efficiency and performance.
Innovation Solution
The surface emitting laser design incorporates a tunnel junction with n-type and p-type semiconductor layers, where the p-type semiconductor layer is composed of multiple regions with different carrier concentrations and band gaps, and includes composition gradient layers and spacer layers to optimize the tunnel junction's resistance and light emission characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional tunnel junction with single-layer p-type semiconductor is used, then the structure is simple, but the voltage drop at the tunnel junction is large
Solution Approach 1:
The p-type semiconductor layer is divided into multiple regions (first p-type semiconductor region, second p-type semiconductor region, and third p-type semiconductor region) with different carrier concentrations. This segmentation allows each region to contribute differently to the tunneling process, reducing the overall voltage drop while maintaining structural feasibility.
Solution Approach 2:
Different regions of the p-type semiconductor layer are assigned different local properties (carrier concentrations) optimized for specific functions. The first region has high carrier concentration for efficient tunneling, the second region has intermediate concentration for transition, and the third region has low concentration for current blocking, thereby reducing voltage drop through localized optimization.
2Loss of energy
If the carrier concentration of the p-type semiconductor layer is increased to reduce voltage drop, then the voltage drop decreases, but the light emission characteristics deteriorate
Solution Approach 1:
The p-type semiconductor layer is segmented into multiple regions with different carrier concentrations, allowing the high carrier concentration to be confined to specific regions (first and third regions) that do not directly participate in light emission, while the second region maintains lower concentration for better light emission characteristics.
Solution Approach 2:
Different local regions are assigned different carrier concentrations based on their functional requirements. The first p-type region has high carrier concentration for tunneling efficiency, the second region has intermediate concentration for balanced performance, and the third region has low concentration to preserve light emission, thus resolving the contradiction between voltage drop reduction and light emission quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces voltage drops at the tunnel junction, enhancing the surface emitting laser's light emission characteristics and overall performance.
Implementation Method 1
a tunnel junction disposed between first and second active layers adjacent to each other in a lamination direction among the plurality of active layers, in which the tunnel junction includes an n-type semiconductor layer and a p-type semiconductor layer laminated together
Data Source
AI summary
The present technology provides a surface emitting laser capable of reducing a voltage drop at a tunnel junction.The present technology provides a surface emitting laser including: first and second multilayer film reflectors (102, 112) laminated together; a plurality of active layers laminated together between the first and second multilayer film reflectors (102, 112); and a tunnel junction (107) disposed between first and second active layers (104, 110) adjacent to each other in a lamination direction among the plurality of active layers, in which the tunnel junction (107) includes an n-type semiconductor layer (107b) and a p-type semiconductor layer (107a) laminated together, and the p-type semiconductor layer (107a) includes first and second p-type semiconductor regions (107a1, 107a2) laminated together.