Surface-Mount Connector Pin Layout for Low-Crosstalk PCB Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current surface mount connections with 'belly-to-belly' arrangements on PCBs face issues of cross-talk and impedance discontinuities due to the proximity of RX and TX vias on opposite sides of the board, leading to signal attenuation and SERDES eye closure, especially in high-density optics applications.
Innovation Solution
The use of connectors with pins arranged in different directions, such as combining 'J-formed' and 'L-formed' pins, allows for optimized trace routes and separation of layer transition vias, reducing cross-talk and impedance discontinuities by providing a parallel solderable surface and minimizing microstrip routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If belly-to-belly connector arrangement is used on PCB, then high-density optics connections are achieved, but cross-talk between RX and TX vias increases due to their proximity
Solution Approach 1:
The patent applies asymmetry by using different pin bend directions (J-formed vs L-formed) for RX and TX signals. RX pins bend in one direction while TX pins bend in the opposite direction, causing their respective vias to exit at different locations on the PCB. This asymmetric arrangement separates RX and TX vias horizontally, reducing cross-talk while maintaining the belly-to-belly connector configuration for high-density connections.
2Ease of manufacture
If all pins are formed as L-bend in a row, then manufacturing is simplified, but the high-speed area becomes crowded with GND return vias and anti-pad spacing requirements
Solution Approach 1:
The patent segments the pin configurations within each row by combining both J-formed and L-formed pins. Instead of using a uniform L-bend for all pins, the row is divided into different pin types with different bend directions. This segmentation allows GND return vias and signal vias to be distributed more evenly across the connector area, reducing via crowding and anti-pad spacing requirements while maintaining manufacturability.
3Object-affected harmful factors
If extended microstrip traces are used to separate RX and TX vias, then cross-talk is reduced, but impedance control accuracy deteriorates and trace length increases
Solution Approach 1:
The patent transitions from vertical separation (using extended microstrip traces in the same location) to horizontal separation (using different pin bend directions to exit vias at different lateral positions). By changing the dimension of separation from vertical extension to horizontal distribution, the solution reduces cross-talk through spatial separation while minimizing the length of surface traces, thereby maintaining better impedance control.
4Ease of manufacture
If vias are positioned at the heel of the pin and footprint pad, then connection is achieved, but stubs form in the signal path causing signal reflections
Solution Approach 1:
The patent applies preliminary action by strategically positioning vias at the toe rather than the heel of the pin during the design stage. This preliminary placement decision prevents stub formation in the signal path before manufacturing occurs. By anticipating and preventing the reflection issue through proper via positioning, the solution maintains signal integrity while remaining compatible with standard manufacturing processes.
Data Source
AI summary
Aspects of the subject disclosure may include, for example, a device including a connector having a connector body and one or more rows of pins, where the connector facilitates a pluggable connection to an electrical cable or pluggable transceiver, where at least one of the one or more rows of pins includes a first group of the pins extending in a first direction and a second group of the pins extending in a second, different direction. The device includes a host board having vias, where at least a portion of the first and second groups of pins are connected with a portion of the vias by way of solder joints. Other embodiments are disclosed.


