Surface Mount Semiconductor Device With Embedded Interconnects
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Solution Overview
Problem
Current semiconductor device packaging techniques face challenges in reducing size while maintaining complex electrical connections, particularly in redistributing connections between semiconductor dies and external circuits, and require precise alignment and additional process steps for complex geometries.
Innovation Solution
The method involves embedding semiconductor dies in a molding compound with intermediate electrical contact elements connected via coated wires and an insulating layer, allowing for geometric redistribution of solder balls or conductive elements on the package surface, enabling flexible connection geometries and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If redistributed chip packaging with multiple electroplating layers is used to achieve complex connection geometries, then connection flexibility is improved, but device complexity and manufacturing process steps increase
Solution Approach 1:
The patent segments the electrical connection function into two distinct parts: (1) embedded electrical contacts within the molding compound that maintain fixed geometric relationships with the die, and (2) exposed electrical contacts on the package surface that can be independently positioned. This segmentation allows each part to be optimized independently, achieving complex connection geometries without requiring complex multi-layer electroplating processes.
Solution Approach 2:
The molding compound serves as an intermediary medium that contains the embedded electrical contacts and positions the exposed electrical contacts. This intermediary structure decouples the geometric constraints between die contact pads and package surface contacts, enabling flexible connection geometries while simplifying the manufacturing process to a single electroplating step.
2Reliability
If wire bonding technique is used to connect die bond pads to exposed electrical contacts, then internal electrical connections are established, but the technique is limited to peripheral contact arrangements
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional electrical connections by embedding contacts within the molding compound volume. This dimensional change allows electrical contacts to be positioned not only around the periphery but also in central and intermediate positions, enabling star-shaped, grid, and other complex connection patterns that cannot be achieved with traditional wire bonding.
3Productivity
If flip-chip technique with solder balls is used to achieve direct die-to-external circuit connections, then connection density is improved, but minimum spacing requirements increase device size
Solution Approach 1:
The patent creates an intermediate copy of the electrical connection interface within the molding compound. The embedded electrical contacts replicate the die bond pad electrical function while allowing different spatial positioning. This copying approach enables high connection density without the minimum spacing constraints of direct solder ball flip-chip techniques, as the exposed electrical contacts can be positioned optimally for external circuit connection.
Data Source
AI summary
A surface mount semiconductor device has a semiconductor die encapsulated in a molding compound. Electrical contact elements of an intermediate set are disposed on the molding compound. A set of coated wires electrically connect bonding pads of the semiconductor die and the electrical contact elements of the intermediate set. A layer of insulating material covers the coated wires, the die and the electrical contact elements of the intermediate set. Electrically conductive elements are exposed at an external surface of the layer of insulating material and contact respective electrical contact elements of the intermediate set through the layer of insulating material.