Surface-Passivated Transistors With Local Conductivity Control
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Solution Overview
Problem
High electron trapping and charge trapping in high power and high frequency semiconductor devices, such as HEMTs, lead to reduced performance and reliability due to high electric fields and charge trapping at the semiconductor-passivation layer interface.
Innovation Solution
A transistor device with modified interface states and non-uniform conductivity regions is achieved by selectively treating and exposing specific areas of the semiconductor structure through surface treatments and passivation layers, creating higher conductivity regions away from the gate to enhance charge control and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiN passivation is employed to alleviate electron trapping, then device performance is improved, but charge trapping remains a concern due to high electric fields
Solution Approach 1:
The patent applies different surface treatments to different regions of the semiconductor structure. Specifically, the first region (gate region) receives a first surface treatment while the second region (drain region) receives a second surface treatment, creating locally optimized properties that address charge trapping in high-field regions while maintaining overall device performance
Solution Approach 2:
The patent modifies surface characteristics by changing physical or chemical parameters through different surface treatments. The treatments alter surface states, interface quality, and electrical properties to reduce charge trapping effects while managing the high electric fields present in HEMT structures
2Ease of manufacture
If uniform passivation is applied across the semiconductor surface, then manufacturing is simplified, but conductivity control and leakage reduction are compromised
Solution Approach 1:
The patent implements non-uniform surface treatment where different regions receive different treatments optimized for their specific functional requirements. The first region (gate area) and second region (drain area) are treated differently to achieve optimal conductivity control and leakage reduction while maintaining manufacturability through a systematic process
Solution Approach 2:
The patent divides the semiconductor surface into distinct regions (first region and second region) that are processed separately with different surface treatments. This segmentation allows for optimized control of conductivity and leakage current in each region while maintaining overall device performance
Data Source
AI summary
A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.