Surface Tessellation Using Differential Flatness Tolerances

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Solution Overview

Problem

Conventional tessellation methods for rendering vector graphics on raster-based devices result in excessive computational resources being used, as they maintain uniform complexity across surfaces, leading to unnecessary polygon density, especially on the interior of patches, which is not perceptually significant to human vision.

Innovation Solution

Implementing a differential flatness tolerance approach where a smaller flatness tolerance is applied to exterior edges and a larger tolerance to interior edges during the recursive subdivision of surfaces, allowing for varying polygon density based on the region, thereby optimizing computational resources by reducing unnecessary polygon density on the interior.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If uniform flatness parameter is used throughout the patch for tessellation, then the tessellation is simple to implement, but the computational resources scale with unnecessary polygon density in the interior

Engineering Contradiction:
Improvetessellation implementation simplicityVSAvoidrendering efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies different flatness tolerances to different regions of the patch: a first (stricter) flatness tolerance for exterior edges and a second (more lenient) flatness tolerance for interior edges. This local differentiation reduces polygon density in the interior where high precision is not visually necessary, thereby reducing computational resources while maintaining visual quality at boundaries.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If stricter flatness tolerance is applied to interior edges, then the surface approximation precision is improved, but the number of polygons increases unnecessarily

Engineering Contradiction:
Improvesurface approximation precisionVSAvoidpolygon density
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent recognizes that exterior edges require higher precision (stricter flatness tolerance) to accurately represent the boundary of the patch, while interior edges can tolerate lower precision (more lenient flatness tolerance) since they are not visually significant. This local quality differentiation maintains necessary precision at boundaries while reducing overall polygon density.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If more polygons are used throughout the patch, then the visual accuracy is improved, but the computational resources required increase

Engineering Contradiction:
Improvevisual accuracyVSAvoidcomputational resources
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies computational resources selectively: stricter flatness tolerance (more polygons) at exterior edges where visual accuracy matters, and more lenient flatness tolerance (fewer polygons) in the interior where visual differences are imperceptible. This optimized resource allocation maintains visual accuracy where needed while reducing overall computational burden.

Inventive Principle:
Principle #3Local quality

4Stability of the object's composition

If uniform tessellation density is maintained, then the rendering is consistent across the surface, but the exterior boundary accuracy may be compromised

Engineering Contradiction:
Improvetessellation consistencyVSAvoidboundary accuracy
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The patent differentiates tessellation requirements by location: exterior edges receive stricter flatness tolerance to ensure accurate boundary representation, while interior regions use more lenient tolerances. This approach maintains tessellation consistency in the interior while prioritizing boundary accuracy where it matters most for visual fidelity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8217936B1Minimizing tessellation of surfaces
Publication Date: 2012.07.10 ADOBE INC
  • US8217936B1 patent drawing
  • US8217936B1 patent drawing
  • US8217936B1 patent drawing

AI summary

A method, system, and computer-readable storage medium are disclosed for minimizing tessellation of surfaces. A first plurality of polygons may be generated, wherein the first plurality of polygons are adjacent to a plurality of exterior curves of a surface. Each of the first plurality of polygons comprises at least one outside edge approximating a portion of one of the exterior curves within a first flatness tolerance. A second plurality of polygons may be generated, wherein the second plurality of polygons are on the interior of the surface. Each of the second plurality of polygons comprises a plurality of inside edges approximating portions of interior curves of the surface within a second flatness tolerance. The first flatness tolerance may be smaller than the second flatness tolerance.