Surface Tunneling Micro Electron Source Planar Structure
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Solution Overview
Problem
Conventional tunneling electron sources have low emission efficiency and are difficult to integrate into large-scale arrays due to their vertically-stacked multi-layer structures, which lead to electron scattering and complex micro-fabrication requirements.
Innovation Solution
A surface tunneling micro electron source with a planar multi-region structure, featuring conductive regions and an insulating region on an insulating substrate, where the minimum spacing between conductive regions is less than 100 nm, allowing for efficient electron tunneling and emission into vacuum with improved emission efficiency and simplified integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertically-stacked multi-layer structure (MIM or SIS) is used for tunneling electron source, then electron tunneling can be achieved, but electron scattering occurs in the second metal or semiconductor layer resulting in low emission efficiency
Solution Approach 1:
The patent transitions from a vertical multi-layer structure to a planar surface structure. The tunneling electron source is formed on the surface of a substrate with conductive regions and insulating regions arranged in a planar configuration rather than stacked vertically. This dimensional change eliminates the need for electrons to pass through a thick second metal layer, reducing scattering and improving emission efficiency while maintaining tunneling capability.
2Reliability
If a vertically-stacked multi-layer structure is used for tunneling electron source, then electron tunneling can be achieved, but the micro-fabrication process becomes complex making large-scale array integration difficult
Solution Approach 1:
The patent simplifies the fabrication process by adopting a planar surface structure that can be formed using standard semiconductor processing techniques such as photolithography, sputtering, and etching. The conductive and insulating regions are patterned on the substrate surface in a two-dimensional arrangement, avoiding the complex alignment and stacking required for vertical multi-layer structures, thereby enabling large-scale array integration.
3Productivity
If the spacing between conductive regions is reduced to less than 100 nm, then emission efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the spacing between conductive regions to be less than 100 nm, a critical parameter change that enables high emission efficiency by enhancing quantum tunneling probability. This precise spacing control is achieved through advanced photolithography and atomic layer deposition techniques, balancing the need for high efficiency with manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The surface tunneling micro electron source achieves emission efficiencies greater than 50% and facilitates large-scale array integration, overcoming the limitations of conventional tunneling electron sources by reducing electron scattering and simplifying the fabrication process.
Implementation Method 1
The tunneling electron source is an electron source based on an internal quantum tunneling effect... electrons in the first metal layer can pass through the insulating layer and enter into the second metal layer due to the quantum tunneling effect
Data Source
AI summary
A tunneling electro source, an array thereof and methods for making the same are provided. The tunneling electron source is a surface tunneling micro electron source having a planar multi-region structure. The tunneling electron source includes an insulating substrate, and two conductive regions and one insulating region arranged on a surface of the insulating substrate. The insulating region is arranged between the two conductive regions and abuts on the two conductive regions. Minimum spacing between the two conductive regions, which equals to a minimum width of the insulating region, is less than 100 nm.