Surrogate Processing Circuitry for Interrupt Latency in Deep Power States
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Solution Overview
Problem
Modern processors with multiple cores face latency issues due to deep power saving states, leading to increased energy consumption and performance degradation in real-time and cloud computing systems, especially in virtualized environments where interrupts cause cores to wake up from deep idle states, resulting in higher tail-latency for I/O traffic.
Innovation Solution
Implementing a processing device with an interface to receive information about the operation state of surrogate processing circuitry, allowing for the redirection of interrupts to either the processing circuitry or the surrogate circuitry based on their states, thereby preventing undesired changes in operation state and maintaining cores in deep power-saving states without incurring interrupt latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If cores enter deep power saving states, then energy consumption is reduced, but interrupt handling latency increases
Solution Approach 1:
The system segments interrupt handling by introducing a surrogate processing circuitry that handles interrupts separately from the main processing cores. This allows cores to remain in deep power saving states while the surrogate circuitry processes interrupts, resolving the contradiction between energy savings and interrupt latency.
Solution Approach 2:
The patent introduces a surrogate processing circuitry as an intermediary component between the interrupt source and the main processing cores. This intermediary handles interrupt processing without requiring cores to exit deep power saving states, thus maintaining low energy consumption while reducing interrupt latency.
2Speed
If cores are kept active to avoid interrupt latency, then interrupt handling speed is improved, but energy consumption increases
Solution Approach 1:
The patent extracts the interrupt handling function from the main processing cores and assigns it to a dedicated surrogate processing circuitry. This extraction allows cores to enter deep power saving states while interrupt handling speed is maintained by the surrogate circuitry, resolving the contradiction between speed and energy consumption.
Solution Approach 2:
The surrogate processing circuitry acts as a copy or replica of the core's interrupt handling capability. This copying enables interrupt processing to occur independently without requiring the main cores to remain active, thus improving interrupt handling speed while reducing energy consumption.
3Use of energy by moving object
If interrupts are redirected to surrogate processing circuitry, then core power saving is improved, but system complexity increases
Solution Approach 1:
The surrogate processing circuitry is designed with multi-functionality, handling both interrupt processing and coordination with the main cores. This universal design reduces the need for additional dedicated components, thereby improving core power saving while minimizing the increase in system complexity.
Solution Approach 2:
The patent merges the surrogate processing circuitry with the existing core architecture, integrating interrupt handling functionality into the overall system rather than adding completely separate components. This merging approach improves core power saving while keeping system complexity manageable through consolidation.
Data Source
AI summary
A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to control the interface and to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.