3D One-Transistor Memory Cell With Surrounding Channel Layout
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Solution Overview
Problem
The challenge of increasing memory density and capacity in integrated circuits (ICs) while optimizing fabrication and performance of memory components is significant, particularly in the context of shrinking transistor sizes.
Innovation Solution
The implementation of a three-dimensional (3D) memory array with one-transistor memory cells featuring a channel region surrounding source and drain regions, utilizing a stack of conductive and insulator materials, and incorporating hysteretic materials to enhance memory cell functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to increase memory density, then memory capacity increases, but fabrication optimization and performance become more difficult to maintain
Solution Approach 1:
The patent implements a three-dimensional memory array structure where multiple memory cells are stacked vertically across multiple substrates, transitioning from planar to vertical arrangement. This dimensional change enables increased memory capacity without proportionally reducing individual transistor size, thereby maintaining fabrication complexity at manageable levels while achieving higher memory density through vertical integration
2Quantity of substance
If transistor size is reduced to increase memory density, then memory capacity increases, but performance optimization becomes more difficult
Solution Approach 1:
By stacking memory cells vertically across multiple substrates connected by interconnect structures, the patent achieves higher memory density without the performance penalties typically associated with scaled transistors. The three-dimensional architecture allows for optimized signal paths and reduced interference between adjacent cells, maintaining performance while increasing capacity
3Quantity of substance
If multiple memory cells are stacked to increase capacity, then memory density increases, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple discrete memory cells, each with its own transistor and storage element, arranged in a three-dimensional configuration. This segmentation allows for modular design and independent optimization of each cell while achieving high overall density through vertical stacking
Solution Approach 2:
The patent implements a nested structure where multiple memory cells are stacked within a single package, with each cell containing its own transistor, storage element, and interconnect structures. This nesting approach increases memory capacity without proportionally increasing the external footprint or overall device complexity
Data Source
AI summary
A three-dimensional (3D) memory array may include one-transistor memory cells with a channel around source and drain regions. In one example, a memory cell includes a transistor with a source region, a drain region, an insulator material between the source region and the drain region in a plane substantially parallel to a substrate, a semiconductor material (e.g., a channel region) surrounding the source region and the drain region in the plane, and a hysteretic material surrounding the semiconductor material in the plane. A first conductive line may be coupled with the source region, a second conductive line may be coupled with the drain region, and a third conductive line including a portion of conductive material may surround the hysteretic material in the plane.