Surround Gate Transistor Composite Structure for Extended Gate Length
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in forming transistors with varying gate lengths on a single chip, as the basic structure of Surrounding Gate Transistors (SGTs) makes it difficult to achieve gate lengths greater than the minimum gate length of a unit SGT, which is necessary for both high-speed logic circuits and I/O sections operating at different voltages.
Innovation Solution
The semiconductor device comprises multiple MOS transistors connected in series and parallel configurations, with pillar-shaped semiconductor layers and shared gate electrodes, allowing for extended gate electrode lengths up to four times that of a unit SGT, enhancing drive current and accommodating different voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple transistors with different gate lengths are formed on a single chip, then both high-speed logic circuits and I/O sections can be integrated, but the basic structure of unit SGT makes it difficult to achieve gate lengths greater than the minimum gate length
Solution Approach 1:
The transistor structure is divided into multiple unit SGTs connected in series. Each unit SGT has its own gate electrode, and by connecting multiple units in series, the total gate length is extended while maintaining the simple unit structure. This segmentation allows gate length variation without complicating the basic SGT design.
Solution Approach 2:
The patent creates a universal transistor structure that can function with different gate lengths by simply varying the number of unit SGTs connected in series. The same basic SGT design serves multiple functions - it can be used for minimum gate length applications or extended to longer gate lengths by adding more units, providing multi-functionality across different operating voltage requirements.
2Power
If transistors with longer gate lengths are used for I/O sections, then higher operating voltages can be achieved, but the occupancy area increases compared to minimum gate length transistors
Solution Approach 1:
Instead of extending gate length in the planar dimension which increases occupancy area, the patent uses the vertical dimension by stacking multiple unit SGTs in series. This dimensional transition allows gate length extension without proportionally increasing the footprint area, as the additional gate length is achieved through vertical stacking rather than lateral expansion.
Solution Approach 2:
Multiple unit SGTs are nested in a series configuration where each unit is integrated within the same vertical structure. This nesting allows the transistors to share common infrastructure such as source and drain regions, reducing the overall occupancy area compared to having separate discrete transistors for each gate length requirement.
3Productivity
If multiple transistors with different gate lengths are integrated on a single chip, then operational efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent achieves different gate lengths by changing the parameter of the number of unit SGTs connected in series, rather than designing entirely different transistor structures. By simply varying this parameter (1 unit, 2 units, 3 units, or 4 units in series), the gate length can be adjusted to meet different operational requirements, improving productivity without significantly increasing device complexity.
Data Source
AI summary
In a vertical transistor comprising a pillar-shaped semiconductor layer and a gate electrode formed around the pillar-shaped semiconductor layer, it is difficult to form a transistor having a gate length greater than that of the vertical transistor. The present invention provides a semiconductor device which comprises two vertical transistors comprising first and second pillar-shaped semiconductor layers each formed on a first diffusion layer on a substrate. The vertical transistors have a common gate electrode. A first upper diffusion layer formed on a top of the first pillar-shaped semiconductor layer is connected to a source electrode, and a second upper diffusion layer formed on a top of the second pillar-shaped semiconductor layer is connected to a drain electrode. The vertical transistors are connected in series to operate as a composite transistor having a gate length two times greater than that of each of the vertical transistors.