Surround Gate Transistor with Silicon-On-Insulator Isolation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in scaling down memory cell size due to limitations in lithographic capabilities, particularly in fabricating DRAM, Flash, and embedded memory devices that require scalable transistor structures.
Innovation Solution
The development of a transistor surround gate structure fabricated using partial and full silicon-on-insulator techniques, which allows for the creation of a scalable memory cell design without the need for a storage capacitor, utilizing shallow trench isolation and nitride spacer etches to form a polysilicon fill material that surrounds the transistor channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional transistor structures are used in DRAM, then the memory cell can store data using a transistor and capacitor, but the memory cell size cannot be scaled down further due to lithographic limitations
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional surround gate structure where the gate electrode wraps around the channel region. This dimensional change allows the gate to contact the channel from multiple directions (top, bottom, and sidewalls), effectively increasing the gate-channel interaction area without proportionally increasing the lithographic footprint. The surround gate configuration enables continued scaling of memory cell size beyond conventional lithographic limits by utilizing vertical and lateral spatial dimensions.
Solution Approach 2:
The gate electrode is positioned to surround and enclose the channel region, creating a nested configuration where the gate wraps around the channel. This nesting arrangement allows the gate structure to be integrated within the same footprint as traditional planar transistors while providing enhanced control over the channel through multiple contact points, thereby reducing the effective memory cell size without compromising manufacturing feasibility.
2Reliability
If the gate electrode surrounds the channel region, then control over the channel is enhanced, but the fabrication process complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: first forming the channel region and shallow trench isolation, then depositing the gate electrode material, followed by patterning to create the surround gate structure, and finally forming the source and drain regions. This segmentation of the fabrication process into manageable steps, each with specific objectives, reduces overall process complexity while achieving the enhanced channel control provided by the surround gate configuration.
Solution Approach 2:
The channel region and shallow trench isolation structures are formed in advance before the gate electrode is deposited and patterned. This preliminary formation of the channel and isolation structures provides a prepared substrate that guides subsequent gate fabrication steps, simplifying the overall process by establishing the geometric framework early in the fabrication sequence.
Data Source
AI summary
A transistor surround gate structure and a method of forming thereof on a semiconductor assembly are described. The transistor surround gate structure is formed on a partial silicon-on-insulator in one direction and on a full silicon-on insulator in a second direction and may be scaled to 4f2 line width for a memory array. A plurality of transistor surround gate structures are utilized as memory storage cells in various memory device applications, such as a dynamic random access memory application, a flash memory application and a single transistor memory cell is utilized in an embedded memory device application, which provide for the use of any one of the memory device applications to be used in a system.