Surround Gate Transistors with Offset Bit Lines
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Solution Overview
Problem
Conventional MOSFET technologies face challenges in forming shallow junctions and managing short channel effects in deep sub-micron transistors, leading to high doping requirements that increase leakage and reduce carrier mobility, particularly in low voltage and low power CMOS circuits like DRAMs.
Innovation Solution
The development of a vertical annular semiconductive transistor body with a surround gate structure and offset alignment from data/bit lines, allowing for a continuous conductive path and reduced need for high doping levels, which is fabricated using a solid phase epitaxial growth process to achieve ultra-thin dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If channel length is reduced to improve performance, then switching speed is improved, but carrier mobility decreases and leakage increases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor body structure. The transistor body extends vertically from the substrate surface, creating a three-dimensional configuration where the channel length is reduced in the vertical dimension while maintaining control over short channel effects through the vertical field effect transistor architecture. This dimensional change allows for improved switching speed without proportionally increasing leakage current.
Solution Approach 2:
The patent implements a surround gate structure where the gate electrode is positioned around the transistor body, with the gate dielectric layer nested between the gate electrode and the transistor body. This nested configuration provides enhanced control over the channel region, allowing for better suppression of short channel effects and reduced leakage current while maintaining the benefits of reduced channel length for improved switching speed.
2Manufacturing precision
If high doping levels are used to suppress short channel effects, then threshold voltage control is improved, but leakage current increases and carrier mobility reduces
Solution Approach 1:
The surround gate structure with the gate electrode, gate dielectric layer, and transistor body arranged in a nested configuration provides enhanced electrostatic control over the channel region. This allows for better threshold voltage control through the gate voltage without requiring extremely high doping levels, thereby maintaining lower leakage current and preserving carrier mobility.
Solution Approach 2:
The patent changes the physical and geometric parameters of the transistor structure by implementing a vertical transistor body with reduced channel length and a surround gate configuration. This structural parameter change enables effective threshold voltage control through the gate electrode while avoiding the need for high doping levels that would otherwise be required to suppress short channel effects.
3Length of moving object
If shallow junctions are formed to meet scaling requirements, then junction depth is reduced, but fabrication difficulty increases
Solution Approach 1:
The patent adopts a vertical transistor body structure where the source and drain regions are positioned at different vertical levels relative to the substrate surface. This vertical configuration allows for the formation of shallow junctions in the lateral dimension while maintaining acceptable electrical characteristics through the vertical field effect transistor architecture, thereby reducing fabrication difficulty associated with forming extremely shallow lateral junctions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves sub-threshold leakage characteristics and facilitates aggressive scaling while reducing fabrication complexity and leakage current, enabling more reliable and efficient operation of memory arrays.
Implementation Method 1
growing a single crystalline semiconductive transistor body to extend vertically around the pillar
Data Source
AI summary
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.