Surrounded-Channel Transistor Structure for Low Parasitic Capacitance
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Solution Overview
Problem
Existing transistors face challenges in achieving low parasitic capacitance, high frequency characteristics, stable electrical performance, and low off-state current, while also requiring efficient manufacturing methods that minimize equipment retrofitting costs.
Innovation Solution
A manufacturing method for semiconductor devices involving a series of etching steps using a hard mask layer to form specific openings in a layered structure, including conductors and insulators, with controlled etching rates to create a transistor with a surrounded channel structure and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional transistor structures are used, then manufacturing is simpler, but parasitic capacitance is high and frequency characteristics are poor
Solution Approach 1:
The transistor structure is divided into multiple functional layers including gate electrode, gate insulator, channel formation layer, and source/drain electrodes with insulating films between them. This segmentation allows each component to be optimized independently, reducing parasitic capacitance while maintaining manufacturability through standardized layering processes.
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional configurations with stacked layers and vertical channel formation. By adding the vertical dimension with multiple insulating layers and embedded conductors, the design reduces parasitic capacitance between components while preserving manufacturing simplicity through layer-by-layer fabrication.
2Volume of moving object
If transistor size is reduced for miniaturization, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
Insulating films are formed between the gate electrode and source/drain electrodes during the initial fabrication stages, before final transistor miniaturization. This preliminary action establishes precise spatial relationships and electrical isolation early in the process, enabling subsequent size reduction without compromising manufacturing precision or increasing parasitic capacitance.
3Object-generated harmful factors
If oxide semiconductor materials are used, then off-state current is reduced, but manufacturing equipment retrofitting costs increase
Solution Approach 1:
The transistor design uses oxide semiconductor materials in the channel formation layer that can be deposited using sputtering equipment already present in conventional manufacturing lines. The multi-layer insulator structure and standard electrode configurations allow the same fabrication equipment to produce both conventional and oxide semiconductor transistors, achieving low off-state current without requiring specialized equipment retrofitting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the production of a transistor with low parasitic capacitance, high frequency characteristics, stable electrical performance, and low off-state current, suitable for high-speed operation and reduced manufacturing costs.
Implementation Method 1
a first etching and a second etching are performed using a hard mask layer as a mask to form a first opening, a second opening, and a third opening
Data Source
AI summary
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.