Surrounding Gate Oxide Semiconductor Transistor Leakage Reduction
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Solution Overview
Problem
Oxide semiconductor transistors used in memory devices face challenges in reducing off-leakage current and on-resistance, particularly due to the thickness of the channel region and the type of junctions formed between electrodes and semiconductor regions.
Innovation Solution
The semiconductor device incorporates a surrounding gate transistor design with a core insulating region within the channel, using metallic regions with specific elements like indium, gallium, and zinc, and oxide semiconductor regions with varying electrical resistance to reduce channel thickness and improve contact resistance, along with high-dielectric-constant insulating layers to enhance carrier concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the channel region thickness is reduced to lower off-leakage current, then off-leakage current is reduced, but on-resistance increases
Solution Approach 1:
The patent applies local quality by creating distinct regions with different properties: the channel region has high resistance to reduce off-leakage current, while the source and drain regions have low resistance to reduce on-resistance. This is achieved through selective doping and oxidation processes that create spatially varying electrical properties within the oxide semiconductor layer.
Solution Approach 2:
The oxide semiconductor layer is segmented into functionally distinct regions: a channel region with high resistance for low leakage, and source/drain regions with low resistance for good contact. The gate electrode is also segmented into a surrounding gate structure that wraps around the channel region, providing localized control over the channel properties.
2Object-generated harmful factors
If oxide semiconductor transistor is used to achieve small off-leakage current, then off-leakage current is reduced, but on-resistance reduction is insufficient
Solution Approach 1:
The patent changes key parameters of the oxide semiconductor transistor: the channel thickness is reduced to 10 nm or less to lower off-leakage current, while the source and drain regions are heavily doped or oxidized to maintain low resistance. The gate voltage and electrode configurations are also optimized to simultaneously achieve low leakage and low on-resistance.
3Ease of manufacture
If conventional transistor structure is used, then manufacturing is simpler, but off-leakage current and on-resistance cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional surrounding gate structure where the gate electrode wraps around the channel region. This dimensional change enables better electrical control and performance improvement while maintaining compatibility with existing manufacturing processes through sequential deposition and etching steps.
Data Source
AI summary
A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.