Surrounding Gate Transistor Decoder Circuit Area Reduction
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Solution Overview
Problem
The increasing scale of semiconductor integrated circuits, particularly for leading-edge microprocessor units, requires more efficient transistor designs to minimize area while maintaining isolation and eliminating the need for body terminals, as seen in planar transistors.
Innovation Solution
The implementation of surrounding gate transistors (SGTs) with a silicon pillar structure, where the source, gate, and drain are arranged perpendicular to the substrate, allowing for compact layouts without the need for body terminals and improved isolation between PMOS and NMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar transistors are used with complete isolation between n-well and p-type substrate, then isolation reliability is improved, but device area increases due to required body terminals
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional surrounding gate transistors, where the gate wraps around the channel in a vertical configuration. This dimensional change allows the gate to control the channel from multiple directions, improving isolation and control without requiring additional body terminals, thereby reducing device area while maintaining isolation reliability
Solution Approach 2:
The surrounding gate structure serves multiple functions simultaneously: it provides electrical isolation between n-well and p-type substrate regions, controls the channel current, and eliminates the need for separate body terminals. This multi-functionality resolves the contradiction by achieving isolation reliability without the area penalty of additional terminal structures
2Area of stationary object
If surrounding gate transistors are implemented with vertical arrangement, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into distinct vertical segments: source region, channel region with surrounding gate, and drain region. This segmentation allows each region to be formed through targeted processing steps, simplifying the manufacturing of the complex three-dimensional structure by breaking it down into manageable segments that can be fabricated sequentially
Solution Approach 2:
The gate structure is nested around the channel in a concentric arrangement, with the gate wrapping around the channel region. This nested configuration achieves the three-dimensional surrounding gate effect using a systematic fabrication approach where layers are deposited and etched in a repeating pattern, reducing manufacturing complexity compared to attempting to form the entire structure in a single step
Data Source
AI summary
A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a semiconductor pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a conductive region formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.