Surrounding Gate Transistor Fabrication via Self-Aligned Diffusion

The patent combines the formation of the gate line and pillar-shaped semiconductor layer into a single etching step using one mask pattern. The mask is designed with patterns that define both the gate line position and the pillar-shaped semiconductor layer position simultaneously. This merging of two separate formation processes into one step reduces the total number of masks and process steps while maintaining precise alignment between the gate line and the pillar structure, thereby resolving the contradiction between manufacturing precision and process complexity.

The patent employs self-aligned formation of the diffusion layer with the gate structure. The diffusion layer is formed by etching through the insulating film using the gate structure itself as the alignment reference, eliminating the need for separate alignment processes. This self-alignment ensures that the diffusion layer position is precisely controlled relative to the gate, optimizing the balance between current flow (which benefits from some overlap) and overlap capacitance (which increases with overlap). The process automatically achieves the optimal configuration without requiring additional alignment steps or complex mask designs.

The patent forms the first insulating film around the fin-shaped semiconductor layer in advance, before the gate line and pillar structures are created. This preliminary formation of the insulating film establishes a foundation that will later serve multiple purposes: it provides electrical isolation that reduces parasitic capacitance, and it serves as a structural reference for subsequent etching steps. By preparing this insulating structure beforehand, the patent simplifies later processing steps and achieves the parasitic capacitance reduction effect without requiring complex multi-step insulating film formations.