Surrounding Gate Transistor Layout for Compact NAND Decoder
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of transistors in semiconductor chips leads to space constraints and the need for compact designs, as traditional planar transistors require isolation and body terminals, which occupy more area.
Innovation Solution
The use of surrounding gate transistors (SGTs) with a silicon pillar structure eliminates the need for well isolation and body terminals, allowing for a compact layout by arranging six transistors in a line with perpendicular source, drain, and gate configurations, connected via silicide regions and metal wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar transistors are used with complete isolation of n-well region and p-type silicon substrate, then reliable transistor operation is achieved, but the area occupied by isolation structures and body terminals increases
Solution Approach 1:
The patent extracts and eliminates the isolation structures (n-well region isolation) and body terminals from the transistor structure by using the surrounding gate configuration where the gate electrode extends around the semiconductor layer, providing natural electrical isolation and control without additional isolation structures or body terminals
Solution Approach 2:
The patent transitions from planar transistor geometry to a three-dimensional surrounding gate structure where the gate electrode wraps around the semiconductor layer in multiple directions, enabling better electrical control and isolation in vertical and lateral dimensions simultaneously, thereby reducing the planar area footprint
2Area of stationary object
If six transistors are arranged in a line with perpendicular source, drain, and gate configurations, then area reduction is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the transistor components (source, drain, gate, semiconductor layer) into distinct formed layers that can be independently patterned and positioned, allowing the six transistors to be arranged in a compact linear configuration while maintaining manufacturing feasibility through sequential layer formation
Solution Approach 2:
The patent employs a universal surrounding gate structure that can be replicated for all six transistors in the decoder, using the same gate electrode configuration and semiconductor layer formation processes, thereby reducing manufacturing complexity through process standardization despite the compact arrangement
Data Source
AI summary
A semiconductor device includes a 2-input NAND decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.