Surrounding Gate Transistor for High-Density Memory
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Solution Overview
Problem
The increasing miniaturization of semiconductor integrated circuits, particularly in MOS transistors, leads to challenges in suppressing leak currents and ensuring operational stability due to hot carrier effects and reduced gate capacitance, which affects the reliability and area efficiency of inverter circuits and static memory cells.
Innovation Solution
A high-degree-of-integration static memory cell is designed using a Surrounding Gate Transistor (SGT) structure with an NMOS SGT access transistor and a CMOS structure, where a gate electrode is formed around an island-shaped semiconductor layer, and an arcuate semiconductor is formed around the gate electrode to construct a PMOS load transistor, allowing for a shorter channel length and improved operational stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOS transistors are miniaturized to increase integration degree, then integration density improves, but leak currents increase and reliability deteriorates due to hot carrier effects
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures, where the channel forms a vertical fin extending from the substrate. This dimensional change increases the effective channel area and gate control without increasing the planar footprint, thereby improving integration density while maintaining reliability through enhanced gate electrostatic control over the channel
Solution Approach 2:
The gate structure wraps around the FinFET channel in a surrounding gate configuration, with the gate electrode positioned on both sides and top of the vertical fin. This nested arrangement maximizes gate control over the channel while minimizing device area, resolving the contradiction between high integration density and reliable current control
2Area of moving object
If MOS transistor size is reduced, then circuit area decreases, but gate capacitance reduces leading to reduced operational stability
Solution Approach 1:
By forming vertical fins extending from the substrate, the patent increases the effective channel length and gate capacitance without increasing the planar device area. The three-dimensional FinFET structure provides sufficient gate control capacitance for operational stability while maintaining compact footprint
Solution Approach 2:
The patent employs high-k dielectric materials in the gate insulator layer, which provide higher capacitance per unit area compared to conventional silicon dioxide. This allows the gate to maintain sufficient capacitive coupling with the channel despite reduced device dimensions, ensuring operational stability in compact structures
3Ease of manufacture
If conventional planar structure is used, then manufacturing is simpler, but leak current suppression is insufficient at nano-scale
Solution Approach 1:
The patent employs sequential deposition and anisotropic etching processes to create vertical FinFET structures. The surrounding gate is formed by depositing gate materials conformally on the fin surfaces and performing controlled etch-back, achieving excellent leak current suppression through three-dimensional geometry while using standard semiconductor manufacturing techniques
4Reliability
If gate electrode upper surface is positioned higher than semiconductor layer, then gate control is improved, but manufacturing complexity increases due to additional alignment requirements
Solution Approach 1:
The patent forms the FinFET channel structure and surrounding gate simultaneously using self-aligned processes. The gate materials are deposited conformally on the fin structures, and a single etch-back step defines both the gate length and the relative positioning of gate and channel, eliminating complex alignment steps while maintaining effective gate control
Solution Approach 2:
The surrounding gate structure self-aligns to the FinFET channel through conformal deposition, where the gate automatically positions itself around the vertical fin. This self-aligned approach ensures precise gate-channel registration and effective electrostatic control without requiring additional lithography alignment steps
Data Source
AI summary
A first driver transistor includes a first gate insulating film that surrounds a periphery of a first island-shaped semiconductor, a first gate electrode having a first surface that is in contact with the first gate insulating film, and first and second first-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first island-shaped semiconductor, respectively. A first load transistor includes a second gate insulating film having a first surface that is in contact with a second surface of the first gate electrode, a first arcuate semiconductor formed so as to be in contact with a portion of a second surface of the second gate insulating film, and first and second second-conductivity-type high-concentration semiconductors disposed on the top and bottom of the first arcuate semiconductor, respectively. A first gate line extends from the first gate electrode and is made of the same material as the first gate electrode.