Surrounding Gate Transistor Pillar Structure for Leakage Control
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Solution Overview
Problem
The increasing degree of integration and miniaturization of MOS transistors, particularly in surrounding gate transistors (SGTs), poses challenges in suppressing leak current while maintaining a large ON-current, requiring techniques to reduce resistance in source, drain, and gate components, as well as optimizing pillar-shaped semiconductor dimensions and configurations to minimize production costs.
Innovation Solution
A semiconductor device production method involving the formation of a pillar-shaped semiconductor layer with a metal gate electrode, optimized dielectric films, and metal-semiconductor compounds to reduce resistance and enhance current flow, while accounting for metal contamination and optimizing source, drain, and gate configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the degree of integration and miniaturization of MOS transistors is increased, then the circuit occupancy area is reduced, but the leak current increases and it becomes difficult to suppress
Solution Approach 1:
The gate is segmented to surround the pillar-shaped semiconductor layer from multiple directions, creating a surrounding gate structure. This segmentation allows the gate to control the channel from all sides, effectively suppressing leak current while maintaining a compact footprint area.
Solution Approach 2:
The transistor structure transitions from a planar two-dimensional configuration to a three-dimensional surrounding gate structure. The gate wraps around the semiconductor pillar in the vertical dimension, increasing the effective gate width without proportionally increasing the occupancy area, thereby suppressing leak current through enhanced electric field control.
2Productivity
If a large ON-current is required to flow through a small occupancy area, then the current density increases, but high resistance in source, drain and gate makes it difficult to apply desired voltage
Solution Approach 1:
Metal materials with low resistance are selectively applied to the source, drain, and gate regions. This local quality enhancement reduces the resistance in these critical components, enabling desired voltage to be applied effectively even when high current density is required through the compact structure.
Solution Approach 2:
The transistor employs composite material construction, combining metal materials for source, drain, and gate electrodes with the semiconductor layer. This composite approach leverages the high conductivity of metals to reduce overall resistance while maintaining the compact occupancy area required for high current density operation.
3Object-generated harmful factors
If the diameter of the pillar-shaped semiconductor is reduced to suppress leak current, then the channel cross-section decreases, but short-channel effects increase
Solution Approach 1:
The gate is segmented into multiple sections that surround the pillar-shaped semiconductor layer. This segmentation allows each gate section to independently control a portion of the channel, providing effective electrostatic control even when the pillar diameter is reduced, thereby suppressing both leak current and short-channel effects.
Solution Approach 2:
The gate structure extends into the vertical dimension by surrounding the pillar, increasing the gate width in the radial direction. This dimensional change compensates for the reduced pillar diameter, maintaining adequate channel control and suppressing short-channel effects while allowing smaller cross-sectional dimensions to reduce leak current.
4Ease of manufacture
If the number of production steps is reduced to lower production cost, then manufacturing simplicity increases, but achieving desired gate length, source and drain configurations, and pillar diameter becomes more difficult
Solution Approach 1:
Multiple formation steps are merged into integrated processes. The surrounding gate structure is formed by depositing gate material that automatically conforms to the pillar shape, and source/drain regions are formed in a unified doping process. This merging reduces the total number of discrete steps while maintaining precise control over gate length and structural dimensions.
Solution Approach 2:
The production method employs self-aligned processes where previously formed structures serve as automatic alignment references for subsequent steps. The pillar-shaped semiconductor layer automatically defines the gate position and dimensions, eliminating the need for separate lithography alignment steps and reducing overall process complexity while maintaining manufacturing precision.
Data Source
AI summary
The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.