Surrounding Gate Transistor with Work Function Induced Source Drain Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration of semiconductor integrated circuits, particularly with nano-scale MOS transistors, faces challenges in suppressing leak currents and reducing circuit area due to difficulties in impurity distribution in silicon pillars, necessitating innovative transistor structures.
Innovation Solution
A surrounding gate transistor (SGT) structure is developed where a pillar-shaped semiconductor with low impurity concentration is surrounded by metals with different work functions, inducing charge carriers through work function differences between the metals and silicon, eliminating the need for impurity implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the width of silicon pillar decreases to achieve higher integration, then the area occupied by circuits is reduced, but it becomes more difficult to make impurity present in the silicon pillar
Solution Approach 1:
The patent changes the impurity concentration parameter in the silicon pillar from conventional high levels to ultra-low levels (10^17 cm^-3 or less), fundamentally altering the approach to transistor operation by eliminating the need for impurity-based conductivity control
Solution Approach 2:
The patent replaces the mechanical/chemical process of impurity implantation with an electrical field-based mechanism using work function differences between metal electrodes and silicon to induce charge carriers, eliminating complex manufacturing steps
2Ease of operation
If impurity concentration is decreased to 10^17 cm^-3 or less, then the threshold voltage can be controlled by gate material work function, but it becomes difficult to suppress leak currents
Solution Approach 1:
The patent applies different work function characteristics to different metal electrodes (source/drain metals vs. gate metal) to create localized electrical fields that induce charge carriers only where needed, enabling threshold voltage control while maintaining low leak currents through selective carrier induction
Solution Approach 2:
The patent uses composite metal structures with different work functions in contact with the silicon pillar, creating a multi-material system where each material contributes specific electrical properties to achieve both low threshold voltage and low leak current
3Reliability
If conventional impurity implantation is used in nano-scale silicon pillars, then transistor operation can be achieved, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The patent extracts and removes the impurity implantation step from the manufacturing process entirely, replacing it with a simpler metal deposition process that uses work function differences to achieve the same transistor operation function
Solution Approach 2:
The patent enables the silicon pillar to self-generate charge carriers through the work function difference between metal electrodes and silicon, eliminating the need for external impurity introduction and simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables transistor operation without impurities in the silicon pillar, reducing the complexity of impurity distribution and enhancing transistor performance by utilizing work function differences between metals and silicon to induce carriers, thus achieving efficient transistor operation.
Implementation Method 1
a first metal that surrounds a portion of the first insulator at a first end of the pillar-shaped semiconductor... defines a source/drain region in the pillar-shaped semiconductor... due to a work function difference between the pillar-shaped semiconductor and the first metal
Implementation Method 2
a third metal that surrounds a portion of the first insulator in a region sandwiched between the first metal and the second metal and defines a channel region in the pillar-shaped semiconductor
Data Source
AI summary
A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 1017 cm−3 or less. A first insulator surrounds the pillar-shaped semiconductor and a first metal surrounds a portion of the first insulator at a first end of the pillar-shaped semiconductor. A second metal surrounds a portion of the first insulator at a second end of the pillar-shaped semiconductor, and a third metal surrounds a portion of the first insulator in a region between the first and second metals. The first metal and the second metal are electrically insulated from the third metal. Source/drain regions are defined in the pillar-shaped semiconductor due to a work function difference between the pillar-shaped semiconductor and the first and second metals.