Surrounding Gate Transistors for Compact NAND Circuit Layout
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Solution Overview
Problem
Conventional semiconductor devices with planar transistors require significant area due to the need for well isolation and body terminals, which limits their compactness and efficiency.
Innovation Solution
The use of surrounding gate transistors (SGTs) arranged in a layered manner on a substrate, eliminating the need for well isolation and body terminals, allows for a compact NAND circuit layout with minimal area usage by connecting transistors in specific configurations to optimize space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar transistors with well isolation and body terminals are used, then transistor functionality is ensured, but device area increases
Solution Approach 1:
The patent extracts and removes the well isolation structure and body terminals from the transistor design. By using a surrounding gate structure where the gate electrode completely surrounds the semiconductor layer, the patent eliminates the need for separate well isolation regions and body terminals, thereby reducing device area while maintaining transistor functionality through the surrounding gate's control mechanism
Solution Approach 2:
The patent transitions from a planar two-dimensional transistor layout to a three-dimensional surrounding gate structure. The gate electrode wraps around the semiconductor layer in multiple dimensions, providing control from all sides. This dimensional change allows the gate to effectively control the channel without requiring traditional well isolation and body terminals, thus reducing the area occupied by isolation structures
2Reliability
If well isolation and body terminals are implemented, then transistor electrical isolation is achieved, but layout complexity increases
Solution Approach 1:
The patent removes the well isolation structure and body terminals from the transistor architecture. The surrounding gate structure inherently provides electrical isolation between adjacent transistors through its three-dimensional configuration, eliminating the need for additional isolation layers and terminal connections, thereby simplifying the overall layout
Solution Approach 2:
The surrounding gate structure serves multiple functions simultaneously: it controls the channel current, provides electrical isolation between adjacent transistors, and eliminates the need for separate body terminals. This multi-functionality reduces layout complexity by consolidating what would otherwise require multiple separate structures into a single integrated gate configuration
Data Source
AI summary
A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.