Polycrystalline Silicon Susceptor Conditioning for Uniform Wafer Etching
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Solution Overview
Problem
Conventional methods for etching semiconductor structures face challenges in achieving uniformity due to edge boundary effects, which are exacerbated by disruptions in heat transfer, momentum transport, and mass transport, leading to edge roll-off and non-uniform thickness across the wafer.
Innovation Solution
A processing reactor is conditioned by depositing an engineered polycrystalline silicon surface layer on the susceptor and preheat ring, which is then grooved to increase the surface area, allowing for improved etching uniformity by reducing grain size and enhancing the etch rate, thereby mitigating edge loading effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used in a single-wafer thermal process chamber, then the etching process can be performed, but edge boundary effects occur causing non-uniform thickness and edge roll-off
Solution Approach 1:
A polycrystalline silicon surface layer is deposited on the susceptor to act as an intermediary between the etchant and the semiconductor structure. This layer modifies the interaction at the susceptor-wafer interface, reducing edge boundary effects and improving thickness uniformity during etching.
Solution Approach 2:
The susceptor surface is modified by depositing a polycrystalline silicon layer and creating grooves, changing the physical and chemical parameters of the susceptor surface. This modification alters heat transfer, momentum transport, and mass transport characteristics, thereby reducing edge roll-off and improving etching uniformity.
2Manufacturing precision
If the gap between the wafer edge and susceptor is increased to reduce edge effects, then edge uniformity may improve, but manufacturing tolerances and thermal expansion become limiting factors
Solution Approach 1:
The polycrystalline silicon surface layer on the susceptor acts as a mediator that reduces edge boundary effects without requiring changes to the physical gap dimensions. This approach avoids the manufacturing tolerances and thermal expansion issues associated with adjusting the gap size.
3Volume of moving object
If the pocket height in the susceptor is increased to extend the affected region, then the etching influence extends toward the inner region, but azimuthal thickness uniformity is not improved
Solution Approach 1:
The susceptor surface is given non-uniform local quality through the deposition of a polycrystalline silicon layer with specific groove patterns. This creates localized variations in surface properties that specifically address edge boundary effects while maintaining control over azimuthal thickness uniformity through proper groove geometry and distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased surface area of the polycrystalline silicon layer reduces edge roll-off and improves thickness uniformity across the semiconductor structure, enhancing the etching process by increasing the etch rate and reducing the dependence on gap size and wafer centering.
Implementation Method 1
A stripping etchant is introduced into the processing reactor without a semiconductor structure being disposed on the susceptor to strip a polycrystalline silicon surface layer from the susceptor
Implementation Method 2
A polycrystalline silicon surface layer is deposited on the susceptor without a semiconductor structure being disposed on the susceptor
Implementation Method 3
The grooving etchant contacts the polycrystalline silicon surface layer to produce a surface-modified polycrystalline silicon surface layer
Data Source
AI summary
Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.