Susceptor Hole Pattern for Epitaxial Flatness Control

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Solution Overview

Problem

Epitaxial delta edge roll-off (DERO) in semiconductor wafer processing leads to undesirable flatness issues due to uneven epitaxial growth, particularly near the (311) orientations, where surface atoms hinder silicon precursor delivery, resulting in enhanced growth rates and flatness variations.

Innovation Solution

A susceptor design with strategically positioned holes outside the wafer radius, varying in density and orientation to align with specific crystal lattice directions, reduces azimuthal DERO variation by optimizing gas precursor distribution during epitaxial chemical vapor deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional susceptor design with uniform hole distribution is used, then manufacturing simplicity is maintained, but azimuthal DERO variation increases due to uneven gas precursor distribution near (311) orientations

Engineering Contradiction:
Improveflatness uniformityVSAvoidsusceptor hole pattern complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The susceptor employs a non-uniform hole distribution pattern where hole density varies in specific azimuthal directions. Holes are strategically omitted or reduced in density near the (311) crystal orientations to compensate for the naturally reduced gas precursor delivery in those regions, creating local quality variations that address the specific flatness issues at different wafer locations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The hole pattern breaks the conventional symmetric uniform distribution by introducing asymmetric variations in hole density at different angular positions around the susceptor perimeter. This asymmetric design specifically targets the (311) orientations where DERO is most problematic, creating an intentional imbalance in the gas flow distribution to achieve better overall flatness uniformity.

Inventive Principle:
Principle #4Asymmetry

2Productivity

If gas stream passes near (311) surfaces of the wafer, then epitaxial growth occurs, but surface atoms on (311) planes deplete silicon precursors, resulting in enhanced growth rate and large DERO

Engineering Contradiction:
Improveepitaxial growth rateVSAvoidflatness control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The susceptor hole pattern is designed to preemptively counteract the enhanced growth tendency near (311) surfaces by creating regions of reduced hole density in those specific azimuthal directions. This preliminary adjustment to the gas distribution compensates for the surface atom effects before they cause excessive DERO, preventing the flatness issue rather than correcting it afterward.

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The susceptor design enhances the flatness of semiconductor wafers by reducing DERO variation, ensuring more uniform epitaxial growth and improved matching of edge roll-off with incoming wafer flatness, resulting in better processing outcomes.

Implementation Method 1

Epitaxial chemical vapor deposition is a process for growing a thin layer of material on a semiconductor wafer

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 2

The susceptor, which supports the semiconductor wafer in the deposition chamber during the epitaxial deposition, is rotated during the process to ensure the epitaxial layer grows evenly

Methodology Applied
Scientific EffectCentrifugal force: Centrifugal Force

Data Source

PatentUS8940094B2Methods for fabricating a semiconductor wafer processing device
Publication Date: 2015.01.27 GLOBALWAFERS CO LTD
  • US8940094B2 patent drawing
  • US8940094B2 patent drawing
  • US8940094B2 patent drawing

AI summary

A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.