Suspend Mode Voltage Regulator for Memory Data Retention
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Solution Overview
Problem
Integrated circuits with volatile memory elements face challenges in power-saving modes, as disabling the auxiliary voltage supply can lead to data loss due to insufficient voltage for memory cells, and existing solutions increase silicon area and power dissipation.
Innovation Solution
An integrated circuit design that allows volatile memory cells powered by an auxiliary voltage supply to be powered by a main voltage supply during a suspend mode, using a voltage regulator circuit with transistors and a well bias circuit to maintain data integrity and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the auxiliary voltage supply is disabled to reduce power consumption, then power saving is achieved, but data stored in volatile memory cells is lost
Solution Approach 1:
A suspend mode voltage regulator circuit is introduced as an intermediary power supply mechanism. When the auxiliary voltage supply is disabled, this regulator activates to provide a reduced voltage level specifically to the volatile memory cells, maintaining their operation and data retention while allowing other circuitry to enter low-power mode.
Solution Approach 2:
The patent applies local quality by providing different voltage levels to different parts of the circuit during suspend mode. The volatile memory cells receive a reduced but sufficient voltage level from the suspend mode regulator, while the rest of the circuitry powered by the auxiliary supply enters low-power mode, optimizing power distribution based on local needs.
2Reliability
If existing solutions are used to maintain memory operation during suspend mode, then data integrity is preserved, but silicon area increases
Solution Approach 1:
The suspend mode voltage regulator circuit is merged with the existing auxiliary voltage supply circuitry. The same regulator can operate in two modes: generating the full auxiliary voltage during normal operation and generating the reduced suspend mode voltage when needed, eliminating the need for a completely separate regulator circuit and reducing overall silicon area.
Solution Approach 2:
The voltage regulator circuit is designed with multi-functionality to serve dual purposes. It can generate both the full auxiliary voltage level for normal operation and the reduced voltage level for suspend mode, controlled by a power-down signal. This universal approach avoids duplicating regulator circuitry and minimizes silicon area consumption.
3Reliability
If existing solutions are used to maintain memory operation during suspend mode, then data integrity is preserved, but power dissipation increases
Solution Approach 1:
The patent changes the voltage parameter dynamically based on operational mode. During normal operation, the regulator outputs the full auxiliary voltage level. During suspend mode, it transitions to outputting a reduced voltage level that is sufficient for memory retention but consumes significantly less power, directly addressing the power dissipation issue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables power-saving without data loss by generating a sufficient voltage for memory cells during suspend mode, reducing power consumption, and minimizing silicon area and power dissipation.
Implementation Method 1
a voltage regulator circuit coupled to a power node, including a first transistor coupled between the first voltage supply and the power node and having a gate responsive to a regulation signal
Implementation Method 2
a well bias circuit having an input coupled to receive a power-down signal, a first output coupled to a well region of the first transistor, and a second output coupled to a well region of the second transistor
Data Source
AI summary
An integrated circuit (IC) device includes a first voltage supply for powering first circuitry within the device, a second voltage supply for powering second circuitry within the device, a suspend circuit having an output to generate a power-down signal, and a voltage regulator circuit coupled to a power node. The voltage regulator circuit includes a first transistor coupled between the first voltage supply and the power node and having a gate responsive to a regulation signal, a second transistor coupled between the second voltage supply and the power node and having a gate responsive to the power-down signal, and a well bias circuit having an input coupled to receive the power-down signal, a first output coupled to a well region of the first transistor, and a second output coupled to a well region of the second transistor.


