Suspended Electrode Pad Structure for Low-Parasitic Gate Inputs

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Solution Overview

Problem

In quantum computers, the parasitic capacitance of the electrode pad connected to the gate electrode in low-noise amplifiers is a significant impediment to noise reduction, as it is influenced by the high dielectric constant semiconductor layer under the electrode pad.

Innovation Solution

A semiconductor device configuration is proposed, where nonconductive nanowires are formed two-dimensionally on the substrate to support the electrode pad, creating a gap between the electrode pad and the substrate, thereby reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the gate length is shortened to reduce intrinsic capacitance, then noise characteristics are improved, but parasitic capacitance of the electrode pad remains large due to the high dielectric constant semiconductor layer underneath

Engineering Contradiction:
Improvenoise characteristicsVSAvoidparasitic capacitance of electrode pad
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the electrode pad from direct contact with the substrate by introducing a support structure (nanowires or posts) underneath it. This separation removes the source of parasitic capacitance (the high dielectric constant semiconductor layer) from direct interaction with the electrode pad, thereby reducing the harmful parasitic capacitance while maintaining the shortened gate length for low noise performance

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary support structure (nanowires or posts) between the electrode pad and the substrate. This intermediary element allows the electrode pad to be suspended above the substrate, preventing direct capacitive coupling with the high dielectric constant semiconductor layer while still providing mechanical support and electrical connection pathways

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If the size of the electrode pad is reduced to minimize parasitic capacitance, then capacitance is reduced, but the electrode pad requires a minimum area for electrical connection

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidelectrical connection capability
Core Design Contradiction:
Object-generated harmful factorsVSEase of operation

Solution Approach 1:

The patent resolves the area-capacitance contradiction by transitioning from a two-dimensional planar constraint to a three-dimensional suspended structure. The electrode pad can maintain its necessary lateral dimensions for electrical connection while being elevated in the vertical dimension above the substrate, reducing parasitic capacitance without compromising connection capability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The support structure is segmented into multiple discrete nanowires or posts distributed underneath the electrode pad. This segmentation provides distributed support and electrical connection pathways, allowing the electrode pad to maintain adequate connection area while being suspended to reduce parasitic capacitance

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces parasitic capacitance, leading to lower noise in the signal input to the transistor, thereby enhancing the performance of low-noise amplifiers in quantum computers.

Implementation Method 1

an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires

Methodology Applied
Scientific EffectCapacitance reduction through physical separation: Capacitance

Data Source

PatentEP4276886B1Semiconductor device, amplifier and method for producing semiconductor device
Publication Date: 2025.05.21 FUJITSU LTD
  • EP4276886B1 patent drawingFigure 1~2
  • EP4276886B1 patent drawingFigure 3~4
  • EP4276886B1 patent drawingFigure 5~6

AI summary

A semiconductor device includes a substrate; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate; a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate; an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires; and an extraction electrode connecting the electrode pad and the gate electrode.