Suspended Gate Semiconductor Device Stress Buffering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices, such as planar MOS transistors and FinFETs, suffer from poor performance due to issues like channel current control and severe leakage current, primarily attributed to the structure and fabrication methods used.
Innovation Solution
A fabrication method involving a base substrate with a gate dielectric film, a gate electrode layer, an offset sidewall film, lightly doped regions, sidewall spacers, and source/drain doped regions, where the offset sidewall film is not in direct contact with the substrate and the gate dielectric film acts as a stress buffer, and sidewall spacers cover both the gate electrode and dielectric layers, reducing stress and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOS transistor structure is used, then manufacturing is simple, but channel current control ability is poor and leakage current is severe
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional structure by forming a suspended gate electrode that extends vertically above the substrate. The gate electrode is positioned at a height greater than the thickness of the gate dielectric film, creating a multi-dimensional control structure that improves channel current control while maintaining manufacturing feasibility through standard semiconductor fabrication processes
2Device complexity
If offset sidewall film is formed directly on substrate, then fabrication is simplified, but stress concentration occurs causing device performance degradation
Solution Approach 1:
The patent introduces a gate dielectric film as an intermediary layer between the substrate and the offset sidewall film. This intermediate layer acts as a stress buffer that absorbs and distributes mechanical stress, preventing stress concentration and cracking that would occur if the offset sidewall film were formed directly on the substrate. The gate dielectric film thickness is controlled to be greater than zero to provide adequate stress relief
3Device complexity
If gate electrode is removed completely, then device structure is simplified, but leakage current increases due to exposed source/drain regions
Solution Approach 1:
The patent selectively removes portions of the gate electrode to form openings while retaining sidewall portions of the gate electrode structure. These remaining sidewall portions act as barriers that prevent direct exposure of the source and drain regions, thereby reducing leakage current. The extraction is partial rather than complete, maintaining the necessary blocking function while simplifying the overall structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the performance of semiconductor devices by reducing channel electrical resistance, increasing drive current, and minimizing current leakage, thereby improving overall device performance.
Implementation Method 1
the gate dielectric film acts as a stress buffer
Implementation Method 2
sidewall spacers cover both the gate electrode and dielectric layers, reducing stress and leakage
Data Source
AI summary
Semiconductor device and fabrication method are provided. The fabrication method includes: providing a base substrate having a first gate dielectric film thereon; forming a first gate electrode layer on a portion of the first gate dielectric film; forming an offset sidewall film on the first gate dielectric film and covering sidewalls of the first gate electrode layer; forming lightly doped regions in the base substrate on sides of the first gate electrode layer; removing the offset sidewall film and a portion of the first gate dielectric film to form a first dielectric layer under the first gate electrode layer; forming sidewall spacers; forming source/drain doped regions on sides of the first gate electrode layer; forming a dielectric layer over the source/drain doped regions and the base substrate; and forming a gate opening in the dielectric layer by removing the first gate electrode layer and the first gate dielectric layer.