Hardware Accelerator Chain Using SVA for Segment-Aware Verification
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Solution Overview
Problem
In deduplicated systems, conventional hardware accelerator chains face challenges in efficiently decompressing and verifying data due to differences in data processing between compression regions and individual segments, leading to increased latency and CPU cache detrimental effects.
Innovation Solution
A data-layout-aware hardware accelerator chain is implemented using a Segment Vector Array (SVA) to inform the hardware accelerator which parts of the input buffer to consume, allowing for specific session processing of each data segment, reducing polling and context switch overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hardware accelerator chains are used for decompression and verification, then processing can be offloaded from the CPU, but latency increases and CPU cache efficiency deteriorates due to differences in data processing between compression regions and individual segments
Solution Approach 1:
The patent divides the decompression and verification process into separate sessions: a first session dedicated to decompression operations and a second session dedicated to verification operations. This segmentation allows each session to be optimized for its specific function, reducing context switching overhead and improving overall processing efficiency while maintaining CPU offloading benefits
Solution Approach 2:
The patent introduces an intermediary data structure (decompressed data region) that serves as a buffer between the compression region and individual segments. This intermediary allows the hardware accelerator chain to process data in an optimized sequence without requiring frequent context switches to the CPU, thereby reducing latency while maintaining high throughput
2Productivity
If conventional hardware accelerator chains process entire compression regions, then CPU bandwidth is reduced, but data layout awareness is lost leading to increased context switches and reduced cache efficiency
Solution Approach 1:
The patent segments the processing workload by creating distinct hardware accelerator sessions for decompression and verification. This allows the system to maintain CPU offloading (improving CPU bandwidth availability) while processing individual data segments in an optimized order (improving data processing efficiency and cache utilization)
Solution Approach 2:
The patent implements dynamic session management where the hardware accelerator chain can flexibly switch between processing entire compression regions and processing individual segments based on data layout requirements. This dynamic approach allows the system to adapt to different processing scenarios, maintaining both CPU bandwidth availability and processing efficiency
Data Source
AI summary
A computer implemented method of data decompression and verification includes decompressing a compressed data segment to generate a decompressed data region. The method also includes generating a segment vector array (SVA) including a number of segment vectors corresponding to data segments within the decompressed data region, each segment vector indicating a location and a size of a corresponding data segment. The method also includes transmitting the SVA to a chain plugin module and transmitting segment vector array data to a SVA-based message constructor. The method also includes constructing a SVA-based message including the location and size of data segments within the decompressed data region, and transmitting the SVA-based message to a hardware accelerator. The method also includes performing verification sessions at the hardware accelerator, each verification session corresponding to a specific data segment indicated by the SVA-based message.