Storage Virtualization Controller Data Transmission via Credit Mechanism
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Solution Overview
Problem
In redundant storage virtualization systems, the inter-controller communication channel (ICC) faces challenges in managing data transmission between storage virtualization controllers, leading to potential memory overflow issues when one controller has not finished executing data while the other transmits, affecting system performance and data correctness.
Innovation Solution
A method for transmitting data between storage virtualization controllers using an inter-controller communication channel, where one controller sends a message with a destination address, reads and transmits data, and the other controller stores it according to the address, utilizing PCI-Express bus interfaces to prevent memory overflow by establishing data transmission tables and credit mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission between storage virtualization controllers is performed without coordination, then data transfer speed is improved, but memory overflow occurs when one controller has not finished executing data while the other transmits
Solution Approach 1:
The patent implements a credit-based flow control mechanism where the receiving controller sends credit messages indicating available buffer space to the transmitting controller. The transmitting controller adjusts its data transmission rate based on the credit value received, creating a feedback loop that prevents memory overflow while maintaining high data transfer speeds. This resolves the contradiction by dynamically coordinating transmission based on real-time buffer status.
Solution Approach 2:
The system dynamically adjusts the data transmission rate based on the credit value, which changes over time as buffers are filled and emptied. The transmitting controller can increase transmission when credits are high and slow down or pause when credits are low, making the transmission process adaptive rather than static. This dynamic adjustment prevents overflow while maximizing throughput.
2Productivity
If the inter-controller communication channel transmits data continuously, then productivity is improved, but memory overflow occurs affecting system performance
Solution Approach 1:
The patent introduces credit messages as an intermediary control mechanism between the two controllers. These credit messages carry information about available buffer space and mediate the data transmission process by enabling the transmitting controller to adjust its sending rate. This intermediary layer simplifies memory management by providing explicit coordination signals rather than requiring complex buffer monitoring and control logic.
Solution Approach 2:
The receiving controller performs preliminary action by pre-calculating and sending credit messages before actual data transmission occurs. This allows the transmitting controller to know in advance how much data it can send without causing overflow, enabling efficient batch transmissions while simplifying memory management through advance planning.
3Ease of operation
If storage virtualization controllers operate independently without synchronization, then ease of operation is improved, but data integrity is compromised when failover is required
Solution Approach 1:
The credit-based mechanism provides continuous feedback between controllers about buffer status and data reception capability. This feedback enables automatic coordination without manual intervention or complex synchronization protocols, maintaining controller independence while ensuring data integrity through real-time awareness of each other's state.
Data Source
AI summary
A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention. The two SVCs comprising a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, the second SVC comprises a second bus interface and a second memory, and an inter-controller communication channel (ICC) is established between the first bus interface and the second bus interface, the method comprising the steps of: transmitting, by the second SVC, a message via the ICC through the second bus interface to the first SVC, in which the message comprises a destination address of a block of the second memory, and the block is accessible; reading, by the first SVC, data in the first memory to be transmitted when the first SVC receives the message; transmitting, by the first SVC, the data to be transmitted and the destination address to the second SVC via the ICC through the first bus interface; and storing, by the second SVC, the transmitted data into the second memory according the destination address.


