Supply Voltage Regulator Startup and Fast Response Circuit
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Solution Overview
Problem
Supply voltage regulator (SVR) circuits face a trade-off between achieving low quiescent current (Iq) and fast response time, with additional challenges such as high-voltage protection and robust startup, which are often contradictory and result in increased power consumption and reduced battery life in devices.
Innovation Solution
The SVR circuit architecture incorporates multiple sub-circuits, including a node initialization sub-circuit for robust startup, a high-voltage protection sub-circuit, a fast turn-off sub-circuit, and a fast start-up sub-circuit, utilizing a combination of MOSFETs, diodes, and current sources to manage node initialization, protect against high voltages, and rapidly respond to voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SVR circuit designs are used to achieve fast response time, then response speed improves, but quiescent current consumption increases
Solution Approach 1:
The SVR circuit is divided into multiple functional sub-circuits: a control sub-circuit for voltage regulation, a fast turn-off sub-circuit for rapid response to overvoltage conditions, a fast turn-on sub-circuit for quick startup, and a node initialization sub-circuit for stable initialization. Each sub-circuit is optimized independently to achieve fast response while minimizing overall power consumption.
Solution Approach 2:
The circuit employs dynamic control mechanisms where transistors switch between different operating states based on voltage conditions. The fast turn-off sub-circuit rapidly discharges capacitor nodes when overvoltage is detected, while the fast turn-on sub-circuit quickly charges nodes during startup. This dynamic operation allows the circuit to achieve sub-200μs response time while maintaining low quiescent current during steady-state operation.
2Reliability
If high-voltage protection mechanisms are added to the SVR circuit, then voltage protection improves, but circuit complexity increases
Solution Approach 1:
The node initialization sub-circuit pre-charges or pre-discharges capacitor nodes to appropriate voltage levels before the main regulation begins. This preliminary action ensures that when high-voltage events occur, the protection circuits start from a known safe state, reducing the complexity of continuous monitoring and control during normal operation.
Solution Approach 2:
Capacitor nodes are introduced as intermediary energy storage elements between the input voltage and the regulated output. These capacitors absorb voltage spikes and provide temporary energy storage, simplifying the protection mechanism by using passive energy storage rather than complex active control circuits for high-voltage protection.
3Reliability
If robust startup mechanisms are implemented in the SVR circuit, then startup reliability improves, but power consumption increases
Solution Approach 1:
The node initialization sub-circuit performs preliminary voltage establishment on capacitor nodes during startup, ensuring that the circuit begins operation from a stable, predefined state. This preliminary initialization prevents startup failures and oscillations, improving reliability without requiring continuous high power consumption during normal operation.
Solution Approach 2:
The fast turn-on sub-circuit provides enhanced current during the brief startup period to quickly establish voltage on capacitor nodes, then transitions to normal low-power operation. This periodic high-current action is limited to the startup phase, ensuring robust initialization while maintaining low quiescent current during steady-state operation.
Data Source
AI summary
A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.