Supply Voltage Regulator Startup and Transient Response Circuit
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Solution Overview
Problem
Supply voltage regulator (SVR) circuits face a trade-off between achieving low quiescent current (Iq) and fast response time, with additional challenges including robust startup, high-voltage protection, and rapid transient response, which are often contradictory in existing designs.
Innovation Solution
The SVR circuit architecture incorporates multiple sub-circuits such as node initialization, high-voltage protection, fast turn-off, and fast start-up sub-circuits, utilizing a combination of NMOS and PMOS transistors, diodes, and current sources to manage node initialization, protect against high voltages, and rapidly respond to voltage changes, all implemented on a single semiconductor die or across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SVR circuit designs are used, then the circuit can provide voltage regulation, but the quiescent current is high and response time is slow
Solution Approach 1:
The SVR circuit is divided into multiple functional sub-circuits: a control sub-circuit for voltage regulation, a voltage protection sub-circuit for over-voltage protection, a fast turn-off sub-circuit for rapid response to voltage spikes, a fast turn-on sub-circuit for quick startup, and a node initialization sub-circuit for proper initialization. Each sub-circuit is optimized independently to achieve low quiescent current while maintaining fast response capabilities.
Solution Approach 2:
The circuit employs dynamic control mechanisms where the control sub-circuit continuously monitors output voltage and adjusts the pass transistor gate voltage accordingly. The fast turn-off and fast turn-on sub-circuits provide dynamic response to voltage transients, enabling the circuit to adapt its response characteristics based on operating conditions to maintain both low quiescent current and fast response time.
2Speed
If the circuit is designed for fast response, then response time improves, but quiescent current increases
Solution Approach 1:
The control sub-circuit uses periodic sampling of the output voltage through the feedback network to determine regulation needs. The fast turn-off and fast turn-on sub-circuits are activated only when voltage transients are detected, rather than operating continuously. This periodic activation strategy enables fast response when needed while minimizing quiescent current during normal operation.
Solution Approach 2:
The voltage protection sub-circuit automatically detects and responds to over-voltage conditions without external intervention. The node initialization sub-circuit self-activates during startup to establish proper initial conditions. These self-service mechanisms eliminate the need for continuous monitoring and control, reducing quiescent current while maintaining fast response capabilities.
3Reliability
If multiple protection and control features are added, then reliability improves, but device complexity increases
Solution Approach 1:
Multiple protection and control functions are merged into a unified SVR circuit architecture. The control sub-circuit, voltage protection sub-circuit, fast turn-off sub-circuit, fast turn-on sub-circuit, and node initialization sub-circuit are integrated to share common components such as the pass transistor, feedback network, and power supply connections. This merging approach achieves robust startup and high-voltage protection while minimizing the increase in device complexity through component sharing and functional integration.
Solution Approach 2:
The control sub-circuit serves multiple functions: voltage regulation through feedback control, startup sequencing, and coordination with protection circuits. The fast turn-off and fast turn-on sub-circuits provide both over-voltage protection and rapid transient response. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while improving reliability.
Data Source
AI summary
A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.