Software-Hardware Division for Embedded Systems

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Solution Overview

Problem

Manual determination of software and hardware assignment in embedded systems is challenging due to numerous combinations, requiring a method for automatic S/W-H/W division that considers resource usage, communication bandwidth, and performance.

Innovation Solution

A design support system that calculates software and hardware processing times and circuit scales for each function, using inter-function data-flow graphs to select optimal implementation combinations for software and hardware execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If manual S/W-H/W division is performed, then flexibility in decision-making is maintained, but the complexity of evaluating numerous combinations increases significantly

Engineering Contradiction:
ImproveManual decision-making flexibilityVSAvoidEvaluation complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The system automatically performs S/W-H/W division by having the computing device independently evaluate multiple implementation combinations based on performance metrics, resource usage, and communication bandwidth, eliminating the need for manual evaluation while maintaining optimization quality

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces manual mechanical evaluation processes with automated computational algorithms that systematically assess numerous S/W-H/W division combinations, using software-based performance prediction and resource estimation to substitute human analysis

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If automatic S/W-H/W division is implemented, then evaluation efficiency is improved, but accuracy in selecting optimal combinations may deteriorate without considering function dependencies

Engineering Contradiction:
ImproveEvaluation efficiencyVSAvoidSelection accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent segments the system into distinct functional units with explicit dependency relationships, modeling each function's resource usage and communication requirements separately while maintaining awareness of inter-functional dependencies through the data-flow graph structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system incorporates feedback mechanisms by using predicted performance metrics and actual resource usage to iteratively refine S/W-H/W division decisions, adjusting the allocation based on observed system behavior and dependency constraints

Inventive Principle:
Principle #23Feedback

3Reliability

If all implementation combinations are evaluated, then comprehensive performance analysis is achieved, but the time required for analysis increases

Engineering Contradiction:
ImprovePerformance analysis completenessVSAvoidAnalysis time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary analysis by pre-calculating performance metrics, resource usage estimates, and communication bandwidth requirements for each function before final S/W-H/W division decisions, allowing the system to quickly evaluate combinations without performing complete analysis from scratch

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system evaluates a subset of most promising implementation combinations rather than exhaustively analyzing all possible divisions, using heuristic methods to identify and focus on configurations that are most likely to satisfy performance and resource constraints

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11657197B2Support system and computer readable medium
Publication Date: 2023.05.23 MITSUBISHI ELECTRIC CORP
  • US11657197B2 patent drawing
  • US11657197B2 patent drawing
  • US11657197B2 patent drawing

AI summary

A software studying unit (122) calculates software processing time of each of a plurality of functions in a target source program. A data-flow graph generation unit (121) generates an inter-function data-flow graph of the plurality of functions based on the target source program. A hardware studying unit (130) calculates hardware processing time of each function and a circuit scale of each function by a high-level synthesis for the target source program. An implementation combination selection unit (140) selects, based on the software processing time of each function, the hardware processing time of each function, the circuit scale of each function, and the inter-function data-flow graph, an implementation combination of one or more functions to be implemented by software and one or more functions to be implemented by hardware.