SWAP-Gate Qubit Mapping for Faster Quantum Circuit Simulation
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Solution Overview
Problem
Existing quantum circuit simulators face increased processing times due to the arrangement of qubits, particularly when executing quantum circuits that require exchanges between local and global qubits, leading to inefficiencies in processing time and resource utilization.
Innovation Solution
A method for inserting SWAP gates strategically into quantum circuits to optimize the arrangement of local and global qubits, utilizing a decision diagram-based quantum circuit simulator for parallel processing across multiple arithmetic devices, allowing for the selection of the most efficient method to reduce processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If SWAP gates are inserted to exchange local and global qubits, then processing time is reduced, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by predicting processing times for different qubit arrangement methods using a quantum circuit simulator before actual execution. The system evaluates multiple possible SWAP gate insertion strategies on a smaller-scale quantum circuit that models the target circuit's characteristics, selects the optimal arrangement in advance, and then applies it to the full-scale circuit. This preliminary evaluation prevents suboptimal arrangements that would waste execution time during actual quantum computation.
Solution Approach 2:
The patent uses copying by creating a smaller-scale copy of the target quantum circuit to serve as a model for optimization. This scaled-down version contains the same structural characteristics and qubit arrangement patterns but with fewer qubits, making it computationally feasible to simulate and evaluate multiple SWAP gate strategies. The optimal arrangement discovered through simulating this copy is then transferred to the full-scale circuit, avoiding the need to exhaustively search all possible arrangements of the larger circuit.
2Ease of operation
If multiple methods are evaluated through simulation, then optimal method selection is improved, but resource utilization increases
Solution Approach 1:
The patent applies partial action by evaluating SWAP gate insertion methods on a partial representation of the full problem - specifically, a smaller-scale quantum circuit that captures the essential structural characteristics but uses fewer qubits. This partial simulation requires significantly fewer computational resources than simulating the complete full-scale circuit, yet provides sufficient information to identify the optimal arrangement strategy for the larger system.
Solution Approach 2:
The patent uses parameter changes by modifying the scale parameters of the quantum circuit used for simulation. Instead of simulating the full-scale circuit with all its qubits, the system creates a scaled-down version with reduced qubit count while preserving the relative arrangement patterns and gate structure. This parameter adjustment makes the simulation computationally tractable while maintaining the predictive value for optimizing the full-scale circuit execution.
Data Source
AI summary
A medium storing a program causing a computer to execute: acquiring, for each of methods, a result of executing a second quantum circuit obtained from a first quantum circuit by the method, the first quantum circuit solving a second problem smaller than a first problem of an original quantum circuit, each of the methods exchanging a local qubit and a global qubit in a quantum circuit by inserting a gate into the quantum circuit; selecting any of the methods using the result of executing the second quantum circuit; and acquiring a result of solving the first problem by executing a quantum circuit obtained from the original quantum circuit by the selected method, wherein the methods includes: a method of exchanging qubits so as to reduce a difference between before and after the inserting; and a method of exchanging qubits so as to reduce the number of times of the inserting.