Swappable Logic Partitions for IC Defect Recovery
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing integrated circuits (ICs) due to defects during fabrication, leading to wasted resources as defective IC dies are often discarded or have significant portions blocked, reducing their usability.
Innovation Solution
Implementing swappable logic partitions and a network-on-a-chip (NOC) to remap defective processing elements to spare ones, allowing for efficient recovery of defective IC dies without sacrificing large portions of the die, using a method that includes marking defective elements with a one-time programmable medium and updating NOC routing tables for communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If defective IC dies are discarded, then manufacturing reliability is maintained, but manufacturing cost increases and resource waste occurs
Solution Approach 1:
The IC die is divided into multiple functionally equivalent logic partitions, allowing individual defective partitions to be identified and isolated without affecting the entire die. This segmentation enables selective recovery of functional portions while discarding only the defective segments.
Solution Approach 2:
The patent implements a defect recovery mechanism where defective logic partitions are identified through testing, marked as unusable, and then recovered by remapping their functionality to spare logic partitions. This allows the IC die to be recovered and reused rather than discarded entirely.
2Reliability
If large sections of IC die are blocked to recover defective areas, then defect propagation is prevented, but usable portion of the IC die is substantially reduced
Solution Approach 1:
The IC die is segmented into multiple independent logic partitions with defined boundaries. This allows defects to be contained within specific partitions without requiring blocking of large sections, as the segmentation already provides natural isolation barriers between functional units.
Solution Approach 2:
A network-on-chip (NOC) acts as an intermediary communication infrastructure between logic partitions. The NOC enables selective routing of signals around defective partitions through updated routing tables, preventing defect propagation while maintaining connectivity and preserving usable die area.
3Productivity
If swappable logic partitions with remapping are implemented, then yield recovery is improved, but device complexity increases
Solution Approach 1:
Multiple logic partitions are designed to be functionally equivalent and interchangeable. Each partition can assume the role of any other partition, allowing defective partitions to be replaced by spares without requiring complex custom remapping logic. This universality simplifies the overall system architecture.
Solution Approach 2:
The system implements self-service through automated defect detection, marking, and remapping processes. The IC die autonomously identifies defective partitions through built-in testing, marks them using one-time programmable elements, and performs remapping without requiring external intervention, thereby managing complexity internally.
4Reliability
If one-time programmable marking is used for defective elements, then defect identification is permanent and reliable, but additional manufacturing steps are required
Solution Approach 1:
One-time programmable (OTP) marking elements are pre-integrated into the IC die manufacturing process. The OTP elements are prepared and configured during the standard manufacturing flow, allowing defect marking to occur as a natural extension of existing processes rather than requiring separate additional manufacturing steps.
Data Source
AI summary
A programmable logic device includes an integrated circuit die having a programmable fabric region including N identical programmable logic partitions. In some embodiments, N−1 of the identical programmable logic partitions are user-programmable. In addition, and in some cases, one of the identical programmable logic partitions is a spare logic partition. In some embodiments, the integrated circuit die further includes a network-on-a-chip (NOC) including a vertical NOC (VNOC) and a horizontal NOC (HNOC). By way of example, the N identical programmable logic partitions are configured to communicate exclusively through the NOC. In some embodiments, a defective one of the N−1 identical programmable logic partitions is configured for swapping with the spare logic partition.