Swappable PHY Circuitry for Standard and Advanced Interconnect Regimes
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Solution Overview
Problem
Current die-to-die (D2D) in-package interconnect technologies face challenges in achieving high interconnect wire densities, particularly in standard interconnect regimes, which are lower compared to advanced package interconnect technologies, limiting signal bandwidth and requiring distinct PHY configurations for standard and advanced interconnect regimes.
Innovation Solution
The implementation of a die design with identical PHY circuitry that can be configured to fit either standard or advanced bump configurations, using enable/disable electrical pathways to optimize PHY circuitry usage, allowing the same die to be reused in both advanced and standard packages, and enabling a common logical interface for various interconnect regimes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If distinct PHY configurations are used for standard and advanced interconnect regimes, then interconnect performance is optimized for each regime, but device complexity and development costs increase
Solution Approach 1:
The PHY circuitry is designed with a universal configuration that can operate in both standard and advanced interconnect regimes. The same die includes PHY circuits capable of functioning with different bump configurations (e.g., 110-micron pitch for standard packages and 45-micron pitch for advanced packages), eliminating the need for distinct PHY designs for different interconnect types.
Solution Approach 2:
The PHY circuitry incorporates dynamic enable/disable pathways that allow selective activation of specific PHY circuits based on the interconnect regime being used. This dynamic configuration enables the same die to adapt its PHY usage pattern according to whether it is connected via standard or advanced interconnect, optimizing performance for each regime while maintaining a single unified design.
2Productivity
If the same die is reused for both standard and advanced packages, then development costs and time-to-market are reduced, but interconnect wire density and signal bandwidth may be compromised
Solution Approach 1:
The PHY circuitry is segmented into multiple independent PHY circuits, where each PHY circuit can be independently enabled or disabled. This segmentation allows selective activation of a subset of PHY circuits that matches the interconnect wire density of the specific package type being used, optimizing the balance between reusability and performance.
Solution Approach 2:
The system changes operational parameters by selectively enabling or disabling specific PHY circuits based on the interconnect regime. For advanced packages with higher wire density, more PHY circuits can be enabled to utilize the available bandwidth, while for standard packages, fewer PHY circuits are activated to match the lower wire density, thereby optimizing performance for each configuration.
3Adaptability or versatility
If enable/disable pathways are implemented to optimize PHY usage, then adaptability to different interconnect regimes is improved, but device complexity increases
Solution Approach 1:
The enable/disable pathways are pre-configured during die fabrication, with electrical pathways leading to each PHY circuit that can be selectively activated. This preliminary configuration allows the PHY circuits to be enabled or disabled based on the interconnect regime without requiring complex runtime reconfiguration logic, thereby reducing operational complexity while maintaining adaptability.
Data Source
AI summary
A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.