Swapped Delay Compensation Circuit for Fractional-N PLL Phase Error
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Solution Overview
Problem
Fractional-N phase-locked loops (PLLs) suffer from residual phase errors and noise due to mismatch issues in digital-to-time converters (DTCs), leading to complex calibration requirements and slower PLL settling times.
Innovation Solution
A phase error compensation circuit utilizing two programmable delay circuits and swapping circuits to self-cancel phase errors, eliminating the need for additional calibration by alternating delays between reference and feedback clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a DTC is used to apply delay to reduce residual phase errors, then phase error compensation is improved, but mismatch issues in the DTC cause nonlinear transfer and incorrect output delay
Solution Approach 1:
The system uses itself to calibrate the DTC by feeding back the delayed reference clock through the same DTC path, allowing the system to automatically measure and compensate for DTC nonlinearities without external calibration equipment
Solution Approach 2:
A feedback loop is established where the delayed reference clock is fed back through the DTC and compared with the original reference clock, enabling continuous measurement and correction of DTC delay errors
2Manufacturing precision
If complex hardware or algorithms are added for calibrating the DTC, then DTC linearity is improved, but additional calibration time is required leading to slower PLL settling
Solution Approach 1:
The calibration function is integrated into the normal operation of the PLL, allowing the system to continuously self-calibrate the DTC without requiring separate calibration procedures or additional calibration hardware
Solution Approach 2:
The DTC calibration is performed continuously during normal PLL operation rather than as a separate preliminary step, ensuring the DTC remains accurate throughout the PLL's operational lifetime without interrupting the locking process
3Device complexity
If a single DTC is used for phase error compensation, then device complexity is reduced, but residual phase errors and noise remain due to mismatch issues
Solution Approach 1:
The single DTC is functionally segmented into two separate DTCs, where the first DTC applies delay for phase error compensation and the second DTC feeds back the delayed signal for calibration, allowing each DTC to operate in its optimal linear range
Solution Approach 2:
The calibration dimension is added by introducing a feedback path that operates in parallel with the main signal path, enabling error measurement and correction without interfering with the primary phase compensation function
Data Source
AI summary
A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.