Switching Device Buffer Segmentation for Head-of-Line Blocking

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Solution Overview

Problem

Existing data switching technologies face challenges in minimizing cost while balancing high link speeds, minimal data loss, maximal throughput, fairness in resource allocation, controllable quality of service, scalability, and efficient congestion management, particularly due to issues like head-of-line blocking and inefficient use of buffering resources.

Innovation Solution

A switching device with primary and secondary buffers that conditionally move data packets from the primary buffer to the secondary buffer based on predetermined criteria, such as an empty secondary buffer or congestion conditions, to mitigate head-of-line blocking and optimize buffer utilization, and includes congestion buffers to further reduce blocking issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data packets are stored in a single buffer queue, then the switch structure is simple and cost is minimized, but head-of-line blocking occurs causing congestion and reduced throughput

Engineering Contradiction:
Improvebuffer structure complexityVSAvoiddata throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The single buffer queue is segmented into multiple buffer queues (first buffer queue, second buffer queue, third buffer queue) to eliminate head-of-line blocking. Each buffer queue can independently store data packets for different egress ports, allowing the switch to select packets from multiple queues rather than being blocked by a single queue's head packet.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a one-dimensional single queue structure to a multi-dimensional buffer structure with multiple queues and selective routing. Data packets are routed to appropriate buffer queues based on destination, creating a dimensional expansion in the buffering architecture that enables parallel access paths and eliminates sequential blocking.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If virtual output queues are implemented for each egress port, then head-of-line blocking is resolved, but the number of buffers required becomes extremely large increasing cost

Engineering Contradiction:
Improvedata throughputVSAvoidbuffer resource requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple buffer queues (first, second, third buffer queues) are merged into a unified buffer structure that serves multiple egress ports. Instead of implementing separate virtual output queues for each egress port, the patent combines buffering resources into shared queues that can be selectively accessed, reducing the total number of buffers while maintaining throughput performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The buffer queues are designed with multi-functionality to serve multiple purposes. The same buffer queues can store packets for different egress ports at different times, and the switch controller dynamically routes packets to appropriate queues based on current traffic conditions, making the buffering infrastructure universal rather than dedicated to specific ports.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If buffering resources are provided at input ports, then scalability is improved, but congestion occurs due to head-of-line blocking

Engineering Contradiction:
Improveswitch scalabilityVSAvoiddata throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The switch implements dynamic buffer allocation and packet selection across multiple buffer queues. The switch controller dynamically determines which buffer queue to access based on real-time traffic conditions and destination requirements, transforming the static input buffering approach into a dynamic multi-queue system that adapts to traffic patterns while maintaining scalability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The multiple buffer queues act as intermediaries between the input ports and egress ports. Rather than directly connecting inputs to outputs, the patent introduces multiple intermediate buffer queues that decouple the input and output stages, allowing independent optimization of both scalability and throughput by managing packet flow through the intermediate queue layer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8059671B2Switching device
Publication Date: 2011.11.15 MICRON TECHNOLOGY INC
  • US8059671B2 patent drawing
  • US8059671B2 patent drawing
  • US8059671B2 patent drawing

AI summary

A switching device comprising at least one ingress port and at least one egress port. The switching device is arranged to receive data packets through the at least one ingress port and to forward received data packets to respective ones of the at least one egress port. The switching device further comprises a primary buffer arranged to store data packets received via at least one of the least one ingress ports and a secondary buffer associated with the primary buffer. The switching device is adapted to select a data packet from the primary buffer and if but only if the secondary buffer satisfies a least one first predetermined criterion, transfer the selected data packet to the secondary buffer.