Switch Circuit Dynamic Packet Buffer Allocation

The patent implements dynamic buffer allocation where the shared buffer area is flexibly adjusted based on real-time traffic conditions and egress queue requirements. The control circuit continuously monitors packet forwarding needs and reallocates buffer space between guaranteed and shared areas, enabling the system to adapt to varying traffic patterns without requiring excessive buffer capacity, thus reducing cost while maintaining adequate storage.

The patent changes the parameter of buffer allocation from static to dynamic by introducing a control circuit that adjusts the size of the shared buffer area based on the number of active egress queues and traffic demand. This parameter change allows the system to optimize buffer utilization efficiency, ensuring adequate storage capacity is provided only when needed, thereby avoiding the cost of over-provisioning buffer memory.

The patent segments the packet buffer into two distinct areas: a guaranteed buffer area that provides minimum guaranteed storage space for each egress queue, and a shared buffer area that can be dynamically allocated. This segmentation ensures that each egress queue receives fair and reliable minimum buffer allocation while allowing the shared area to be flexibly distributed based on actual traffic needs, thus maintaining both fairness and high utilization efficiency.

The shared buffer area serves multiple egress queues simultaneously and can be dynamically allocated to different queues based on their current traffic demands. This multi-functional design allows the same buffer resources to be efficiently utilized across multiple queues, improving overall productivity while the guaranteed buffer area maintains reliability through fair distribution.