Switch Control Circuit With Non-Overlapping Enable Timing

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Solution Overview

Problem

Existing switch control circuitry in wireless communication systems faces issues with current surge due to concurrent switching of supply nodes, leading to reduced battery life and potential frequency instability in voltage-controlled oscillators.

Innovation Solution

A circuit comprising flip-flops, a NOR gate, AND gates, and a delay element generates non-overlapping enable signals to control switches, disabling the control mechanism for a specific time period when an enable signal transitions, preventing concurrent switching and reducing current surge.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional switch control circuitry is used to control multiple switches, then the switching operation is simple and fast, but current surge occurs due to concurrent switching of supply nodes

Engineering Contradiction:
Improvecurrent surge preventionVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The delay element introduces a time advance mechanism that disables the control mechanism before concurrent switching can occur. When an enable signal transitions, the delay element proactively generates a disabled state that prevents subsequent switches from activating during the vulnerable transition period, thereby preventing current surge before it happens.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The delay element acts as an intermediary between the enable signals and the control mechanism. It mediates the timing relationship between multiple switches by introducing a controlled delay that ensures sequential operation rather than concurrent switching, thus preventing current surge while maintaining circuit control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If switches are controlled simultaneously without delay, then the control mechanism is simple and responsive, but frequency instability occurs in voltage-controlled oscillators

Engineering Contradiction:
Improveoscillator stabilityVSAvoidcontrol signal delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The delay element performs preliminary action by preemptively disabling the control mechanism during the critical transition period. This preliminary disabling prevents the oscillator from experiencing frequency instability caused by concurrent switching, while the delay duration is carefully controlled to minimize impact on overall system timing.

Inventive Principle:
Principle #10Preliminary action

3Duration of action of moving object

If concurrent switching of supply nodes is allowed, then battery life is reduced due to current surge, but switching speed is maintained

Engineering Contradiction:
Improvebattery lifeVSAvoidswitching speed
Core Design Contradiction:
Duration of action of moving objectVSSpeed

Solution Approach 1:

The delay element serves as a timing intermediary that sequences switch activation. It maintains acceptable switching speed by enabling switches in rapid succession while preventing simultaneous activation that would cause current surge and battery drain, thus optimizing both battery life and switching performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20200389154A1Techniques for generating switch control signals
Publication Date: 2020.12.10 QUALCOMM INC
  • US20200389154A1 patent drawing
  • US20200389154A1 patent drawing
  • US20200389154A1 patent drawing

AI summary

Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.