Switch Data Plane ASIC Power Reduction via Local Caching
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Solution Overview
Problem
Datacenter Ethernet switches consume significant power due to their data plane subsystem, which is the main power consumer, and existing power reduction techniques are general and not specifically tailored to this component.
Innovation Solution
The solution involves a specific architecture and floorplan for the switch data plane ASIC, including interfacing units, data path units, and a network on chip, with local sets of DPUs arranged to minimize packet travel distance and utilize caching for efficient packet processing and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data plane subsystem processes packets through multiple lookup queries and long travel paths, then packet processing completeness is improved, but power consumption increases
Solution Approach 1:
The patent pre-loads forwarding rules and packet metadata into on-chip caches before packets arrive. When packets need processing, the cached information is already available, eliminating the need for time-consuming and power-intensive lookup queries across multiple memory hierarchies. This preliminary preparation of data reduces the active processing time and energy consumption while maintaining complete packet processing capability.
Solution Approach 2:
The patent introduces on-chip caches as intermediary structures between the packet processing logic and main memory. These caches store frequently accessed forwarding rules and packet metadata, acting as a buffer that reduces the distance and energy required for data access. The intermediary caches minimize the need for long travel paths across the chip while ensuring all necessary processing information is readily available.
2Reliability
If the switch uses a detailed floorplan with long packet travel paths, then comprehensive packet processing is achieved, but power consumption increases
Solution Approach 1:
The patent organizes the data plane subsystem with locally cached forwarding rules and metadata stored near the packet processing units that need them. This local storage arrangement eliminates the need for packets to travel long distances across the chip to access processing information. Each processing unit has immediate access to its required data locally, reducing energy loss from long travel paths while maintaining comprehensive processing capability.
Solution Approach 2:
The patent transitions from a traditional hierarchical memory access model to a spatially distributed caching architecture. Instead of accessing memory through a single vertical hierarchy, the system distributes cache memory across the horizontal plane of the chip, close to processing units. This dimensional reorganization reduces the physical travel distance for data access while preserving all necessary processing functions.
3Use of energy by moving object
If general power reduction techniques are applied to the data plane subsystem, then some power savings are achieved, but the techniques are not optimized for this specific component
Solution Approach 1:
The patent changes the fundamental parameters of the data plane subsystem by implementing on-chip caching specifically tailored to switch operations. Rather than applying generic power reduction techniques, the system modifies the memory hierarchy parameters, cache size, and placement to match the specific access patterns and performance requirements of packet switching. This component-specific parameter optimization achieves both power reduction and adaptability to the data plane subsystem's unique characteristics.
Data Source
AI summary
A data plane integrated circuit that includes interfacing units (IFUs), Datapath units (DPUs); and a network on chip (NoC). The DPUs are arranged in local sets of DPUs that are proximate to each other, each local set is configured to (a) store an instance of packet header processing control data structures and (b) independently perform local packet header processing and transmission scheduling.