Software Virtual Switch Data Plane Semantics

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Solution Overview

Problem

Software virtual switches running on general-purpose computing platforms face performance suboptimality due to the lack of semantics in existing declarative languages like P4, which are not designed to leverage the unique features of these platforms, such as Intel Architecture instruction sets, processor performance, and cache layouts.

Innovation Solution

A set of declarative language semantics is introduced to optimize software virtual switch performance by allowing programmers to define data plane functionality, including match-action table assignment to cores, pipeline level core mapping, flow caching, algorithm selection, and priority settings, which can be compiled into machine code for optimal execution on multi-core platforms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If P4 language is used to program software virtual switches, then protocol independence and configurability are improved, but performance optimization on general-purpose computing platforms deteriorates due to lack of platform-specific semantics

Engineering Contradiction:
Improveprotocol independenceVSAvoidpacket processing performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the declarative language into two distinct layers: a platform-independent P4 layer for defining protocol semantics and a platform-specific extension layer for optimizing performance on general-purpose computing platforms. This segmentation allows each layer to fulfill its specific purpose without compromising the other, resolving the contradiction between protocol independence and performance optimization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary compilation process that translates the high-level P4 program with platform-specific annotations into optimized machine code for general-purpose computing platforms. This intermediary layer bridges the gap between the abstract P4 language and the concrete hardware architecture, enabling both protocol independence and performance optimization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If hardware switch architecture is used, then packet processing speed is improved, but configurability and ease of updating protocols deteriorates

Engineering Contradiction:
Improvepacket processing speedVSAvoidconfigurability
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The patent replaces the fixed mechanical hardware switch architecture with a software-based virtual switch running on general-purpose computing platforms. By using software instead of fixed hardware, the system gains configurability and ease of updating while maintaining high performance through platform-specific optimizations and parallel processing capabilities.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If software virtual switch is implemented on general-purpose computing platforms, then configurability is improved, but performance suboptimality occurs due to lack of platform-aware semantics

Engineering Contradiction:
ImproveconfigurabilityVSAvoidpacket processing throughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by allowing different parts of the virtual switch to be optimized for specific platform characteristics. The declarative language enables programmers to specify platform-aware data structures, memory layouts, and processing algorithms that exploit the local qualities of general-purpose computing platforms, such as cache hierarchies and multi-core architectures, thereby improving throughput while maintaining configurability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11409506B2Data plane semantics for software virtual switches
Publication Date: 2022.08.09 INTEL CORP
  • US11409506B2 patent drawing
  • US11409506B2 patent drawing
  • US11409506B2 patent drawing

AI summary

Examples may include a method of compiling a declarative language program for a virtual switch. The method includes parsing the declarative language program, the program defining a plurality of match-action tables (MATs), translating the plurality of MATs into intermediate code, and parsing a core identifier (ID) assigned to each one of the plurality of MATs. When the core IDs of the plurality of MATs are the same, the method includes connecting intermediate code of the plurality of MATs using function calls, and translating the intermediate code of the plurality of MATs into machine code to be executed by a core identified by the core IDs.