Switch Device Packet Loss Detection via Time Comparison

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Solution Overview

Problem

In information processing systems using RDMA, link-down errors can lead to packet loss and data corruption, as the system may incorrectly notify completion of data transfer when link-up occurs after a temporary hardware failure, resulting in incomplete data being processed.

Innovation Solution

A system configuration where the transmitting start time is embedded in packets, allowing switches to compare this time with the link-up time to detect packet loss and prevent the final packet from being delivered if the link-up time is later, thereby avoiding data corruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If RDMA is adopted for high throughput and low latency communication, then communication efficiency is improved, but packet loss detection capability deteriorates because guaranteed delivery is only provided at the link level, not between nodes

Engineering Contradiction:
Improvecommunication throughputVSAvoidpacket loss detection
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an intermediary mechanism (sequence number tracking and time information embedding) between the RDMA communication layers to detect packet losses. The switch device acts as an intermediary that monitors packet arrival times and compares them with transmitted packet times to identify lost packets, thereby extending reliability detection beyond the link level without compromising RDMA's high throughput performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If link-down errors are discarded to prevent packets from staying in the network, then network stability is improved, but data integrity deteriorates when link-up occurs after temporary hardware failure and packets are incorrectly delivered

Engineering Contradiction:
Improvenetwork stabilityVSAvoiddata integrity
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by embedding time information in packets at the transmitting end before potential link-down occurs. This allows the receiving end to later compare arrival times with expected transmission times and detect packet losses due to link-down, preventing incorrect delivery of incomplete data while maintaining network stability during temporary failures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the receiving end sends notifications about packet loss detection back to the transmitting end. This feedback loop allows the system to correct data integrity issues by identifying when packets were lost due to link-down and preventing incorrect completion notifications from reaching higher-level software.

Inventive Principle:
Principle #23Feedback

3Reliability

If sequence numbers are used to detect packet loss, then packet loss detection is improved, but device complexity increases due to additional tracking requirements

Engineering Contradiction:
Improvepacket loss detectionVSAvoidtracking complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the time information embedding and comparison mechanism universal across all packet processing functions in the switch device. The same time tracking and comparison logic serves multiple purposes: detecting packet loss, determining packet arrival order, and identifying incomplete data transfers. This multi-functionality reduces overall device complexity compared to implementing separate dedicated sequence number tracking systems.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9479410B2Information processing system, information processing device, data transfer device, and information processing system control method
Publication Date: 2016.10.25 FUJITSU LTD
  • US9479410B2 patent drawing
  • US9479410B2 patent drawing
  • US9479410B2 patent drawing

AI summary

A processing system includes a first processing device and a switch device. The first processing device includes a first transmitter configured to transmit a plurality of packets, and a controller configured to acquire first time information indicating a first time at which the transmitting of the plurality of packets started. The switch device includes a first receiver configured to receive at least one of the plurality of packets transmitted from the first processing device and receive the first time information from the first processing device, a second transmitter configured to acquire second time information indicating a second time at which a link-up occurred, compare the second time information with the first time information, and perform a notification to a second processing device of occurrence of error in transmitting of the plurality of packets when the second time is later than the first time.