Switch Device Asymmetric Submodule Layout for Current Balancing
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Solution Overview
Problem
Existing power semiconductor switch devices face challenges in optimizing layouts to minimize switching and conduction losses, particularly in applications with multiple input voltages, where achieving balanced current distribution and reduced parasitic stray inductances is crucial.
Innovation Solution
The solution involves a switch device comprising multiple transistor switches with submodules arranged such that at least one submodule is closer to certain second submodules than to others, facilitating balanced current distribution and improved heat dissipation through alternating spatial arrangements, which can be applied in topologies like NPC and ANPC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If submodules are arranged in a conventional layout, then manufacturing is simplified, but current distribution becomes unbalanced and parasitic stray inductances increase
Solution Approach 1:
The patent applies asymmetry by arranging submodules in a non-uniform spatial pattern where at least one submodule is positioned closer to two submodules of another transistor switch than to submodules of its own switch. This asymmetric arrangement optimizes current distribution balance and reduces parasitic stray inductances, resolving the contradiction between simplified manufacturing and balanced current distribution.
2Loss of energy
If load terminals are placed close to each other, then commutation paths are optimized, but layout complexity increases
Solution Approach 1:
The patent applies local quality by optimizing the spatial arrangement of submodules locally within the device structure. Specifically, at least one submodule is positioned closer to two submodules of another transistor switch than to its own submodules, creating localized optimization of commutation paths that reduces conduction losses while maintaining overall layout manageability.
Data Source
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AI summary
A switch device is described including a first transistor switch and a second transistor switch. Each of the first and second transistor switches comprises a plurality of submodules. At least one submodule of the first transistor switch is spatially arranged closer to at least two submodules of the second transistor switch than to other submodules of the first transistor switch.